ram.v

這是一堆verilog的source code.包含許多常用的小電路.還不錯用.

// renoir header_start
//
// Module timing.ram.ram
//
// Created:
//          by - Administrator.UNKNOWN (LMC)
//          at - 03:52:35 PM 01/11/2002
//
// Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
//
// renoir header_end

`resetall
`timescale 1ns/10ps
`define 	Tvavd	10 	// data delay out of memory
`define		Ts2z	5	// delay of deseclt to tristate
module ram(addr, data, sel, rw,clk);
		
	input 	clk;
	input 	[15:0] 	addr;
	inout 	[15:0]	data;
	input 	sel, rw;

	reg 	[15:0]	mem_array	[0:65536], data_internal;
	reg		tprob;


// Internal Declarations
// data bus tri-state. Bi- directional.

	assign data = (sel) ? data_interna :16'bz;

// Always statement that does the actual read and write

	always @ (posedge clk)
    	begin
		//read memory
		if ((rw === 1'b1) && 
		(sel === 1'b1))
		data_internal = mem_array [addr[15:0]];

		//write memory
		if((rw === 1'b0)&&
		(sel === 1'b1))
		mem_array [addr[15:0]] = data;
		end

//The speccify block where all the timing and verification is place.
/********************************************************************/

specify

// Define timing parameter

	specparam	Tclk_period = 20;
	specparam	Tclk_high_min = 9;
	specparam	Tclk_low_min = 7;
	specparam	Taddr_clk_setup = 4;
	specparam	Taddr_clk_hold = 3;
	specparam	Tsel_clk_setup = 4;
	specparam	Tsel_clk_hold = 4;
	specparam	Tclk_data_valid = 12;
	specparam	Trise = 0.5;
	specparam	Tfall = 0.3;
	specparam	T0_to_z = 0.1;
	specparam	Tz_to_1 = 0.3;
	specparam	T1_to_z = 0.1;
	specparam	Tz_to_0 = 0.2;

// Declare module path and apply delay

	if (sel== 0) 
	
	(posedge clk *> data) = (Tclk_data_valid + Trise, Tclk_data_valid + Tfall, 0, 0, 0, 0);
	(negedge sel *> data) = (0, 0, T0_to_z, 0, T1_to_z,0);
	(posedge sel *> data) = (0, 0, 0,Tz_to_1, 0, Tz_to_0);

// Do timing verification like set & hold, ect.

	$period (posedge clk, Tclk_period, tprob);
	$width (posedge clk, Tclk_high_min, 0,tprob);
	$width (negedge clk, Tclk_low_min, 0, tprob);

	$setup (addr, posedge clk, Taddr_clk_setup, tprob);
	$hold (addr, posedge clk, Taddr_clk_hold, tprob);

	$setuphold (sel, posedge clk, Tsel_clk_setup, Tsel_clk_hold, tprob);

	endspecify

	// Report the time of every timing violation

	always @ (tprob)
	begin
		$display (%0d: "Timing violation found", $time);
    end

// renoir interface_end
endmodule