📄 two_d_dct.vwf

📁 altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 11.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 11000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("aclr")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clken")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("serial_data")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("serial_data[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("serial_data[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "serial_data";
}

SIGNAL("data_valid")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dct_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 22;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dct_out[21]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[20]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[19]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[18]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[17]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[16]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

SIGNAL("dct_out[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dct_out";
}

TRANSITION_LIST("aclr")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 96.474;
		LEVEL 0 FOR 10903.526;
	}
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 1;
			NODE
			{
				REPEAT = 220;
				LEVEL 0 FOR 25.0;
				LEVEL 1 FOR 25.0;
			}
		}
	}
}

TRANSITION_LIST("clken")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100.185;
		LEVEL 1 FOR 3215.425;
		LEVEL 0 FOR 7667.773;
		LEVEL 1 FOR 16.617;
	}
}

TRANSITION_LIST("serial_data[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 6498.393;
		LEVEL 1 FOR 4501.607;
	}
}

TRANSITION_LIST("serial_data[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3298.393;
		LEVEL 1 FOR 3200.0;
		LEVEL 0 FOR 3200.0;
		LEVEL 1 FOR 1301.607;
	}
}

TRANSITION_LIST("serial_data[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1698.393;
		LEVEL 1 FOR 1600.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 1600.0;
			LEVEL 1 FOR 1600.0;
		}
		LEVEL 0 FOR 1301.607;
	}
}

TRANSITION_LIST("serial_data[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 898.393;
		LEVEL 1 FOR 800.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 800.0;
			LEVEL 1 FOR 800.0;
		}
		LEVEL 0 FOR 800.0;
		LEVEL 1 FOR 501.607;
	}
}

TRANSITION_LIST("serial_data[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 498.393;
		LEVEL 1 FOR 400.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 0 FOR 400.0;
			LEVEL 1 FOR 400.0;
		}
		LEVEL 0 FOR 400.0;
		LEVEL 1 FOR 101.607;
	}
}

TRANSITION_LIST("serial_data[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 298.393;
		LEVEL 1 FOR 200.0;
		NODE
		{
			REPEAT = 26;
			LEVEL 0 FOR 200.0;
			LEVEL 1 FOR 200.0;
		}
		LEVEL 0 FOR 101.607;
	}
}

TRANSITION_LIST("serial_data[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 198.393;
		LEVEL 1 FOR 100.0;
		NODE
		{
			REPEAT = 53;
			LEVEL 0 FOR 100.0;
			LEVEL 1 FOR 100.0;
		}
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 1.607;
	}
}

TRANSITION_LIST("serial_data[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 148.393;
		LEVEL 1 FOR 50.0;
		NODE
		{
			REPEAT = 108;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 1.607;
	}
}

TRANSITION_LIST("data_valid")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4131.406;
		LEVEL 1 FOR 6868.594;
	}
}

TRANSITION_LIST("dct_out[21]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 6685.275;
		LEVEL 1 FOR 49.75;
		LEVEL 0 FOR 0.353;
		LEVEL 1 FOR 0.251;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 0.044;
		LEVEL 0 FOR 298.399;
		LEVEL 1 FOR 0.73;
		LEVEL 0 FOR 50.086;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.785;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 748.851;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.911;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 299.367;
		LEVEL 1 FOR 49.27;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 0.73;
		LEVEL 0 FOR 50.086;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 615.112;
	}
}

TRANSITION_LIST("dct_out[20]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 6686.49;
		LEVEL 1 FOR 49.75;
		LEVEL 0 FOR 348.315;
		LEVEL 1 FOR 1.391;
		LEVEL 0 FOR 48.827;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 749.802;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.2;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 749.553;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 301.618;
		LEVEL 1 FOR 48.609;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 1.391;
		LEVEL 0 FOR 48.827;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 615.227;
	}
}

TRANSITION_LIST("dct_out[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 6686.199;
		LEVEL 1 FOR 49.75;
		LEVEL 0 FOR 0.329;
		LEVEL 1 FOR 0.251;
		LEVEL 0 FOR 348.212;
		LEVEL 1 FOR 1.004;
		LEVEL 0 FOR 48.747;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 749.454;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.374;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.236;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 301.189;
		LEVEL 1 FOR 48.996;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 1.004;
		LEVEL 0 FOR 48.747;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 615.508;
	}
}

TRANSITION_LIST("dct_out[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4234.086;
		LEVEL 1 FOR 2450.879;
		LEVEL 0 FOR 0.807;
		LEVEL 1 FOR 49.75;
		LEVEL 0 FOR 348.564;
		LEVEL 1 FOR 0.879;
		LEVEL 0 FOR 48.963;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.004;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 751.196;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.091;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 299.746;
		LEVEL 1 FOR 149.121;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 0.879;
		LEVEL 0 FOR 48.963;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 616.072;
	}
}

TRANSITION_LIST("dct_out[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4234.025;
		LEVEL 1 FOR 2451.127;
		LEVEL 0 FOR 50.326;
		LEVEL 1 FOR 0.251;
		LEVEL 0 FOR 348.296;
		LEVEL 1 FOR 1.127;
		LEVEL 0 FOR 849.069;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 750.3;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 749.348;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 301.283;
		LEVEL 1 FOR 148.873;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 50.0;
			LEVEL 1 FOR 50.0;
		}
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 1.127;
12 下一页
💿 文件大小 25 K
👤 上传用户 zyb
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#altera #FPGA #DSP #DCT
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