predecode.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity predecode_ent is
    port (
          clk : in std_logic;
          inst : in std_logic_vector(2 downto 0);
          src1 : in std_logic_vector(3 downto 0);
          src2 : in std_logic_vector(3 downto 0);
          dest : in std_logic_vector(3 downto 0);
          data : in std_logic_vector(31 downto 0);
          flush : in std_logic;
          cmd : out command_type;
          pd_src1 : out register_type;
          pd_src2 : out register_type;
          pd_dest : out register_type;
          pd_data : out std_logic_vector(31 downto 0);
          pd_read : out std_logic
         );
end predecode_ent;

architecture predecode_arch of predecode_ent is
begin
    process(clk, inst, src1, src2, dest, data, flush)
        variable int_command : command_type := NOP;
        variable int_src1 : register_type := reg0;
        variable int_src2 : register_type := reg0;
        variable int_dest : register_type := reg0;

    begin
        if (clk'event and clk = '1') then
            if (flush = '0') then

----decoding inst input into command_type values

                case inst is
                    when "000" =>

----pd_read is set to '1' when an instruction requires reading 
----the values of internal registers

                         pd_read <= '1';
                         int_command := MOVE;
                    when "001" =>
                         pd_read <= '1';
                         int_command := ADD;
                    when "010" =>
                         pd_read <= '1';
                         int_command := SUB;
                    when "011" =>
                         pd_read <= '1';
                         int_command := MUL;
                    when "100" =>
                         pd_read <= '1';
                         int_command := CJE;
                    when "101" =>
                         pd_read <= '0';
                         int_command := LOAD;
                    when "110" =>
                         pd_read <= '1';
                         int_command := READ;
                    when "111" =>
                         pd_read <= '0';
                         int_command := NOP;
                    when others => NULL;
                end case;

----decoding of src1 to determine register used for <src1>
----usage of case statement to represent a huge multiplexer, 
----if statement is not used as it would generate priority encoder

                case src1 is
                    when "0000" => int_src1 := reg0;
                    when "0001" => int_src1 := reg1;
                    when "0010" => int_src1 := reg2;
                    when "0011" => int_src1 := reg3;
                    when "0100" => int_src1 := reg4;
                    when "0101" => int_src1 := reg5;
                    when "0110" => int_src1 := reg6;
                    when "0111" => int_src1 := reg7;
                    when "1000" => int_src1 := reg8;
                    when "1001" => int_src1 := reg9;
                    when "1010" => int_src1 := reg10;
                    when "1011" => int_src1 := reg11;
                    when "1100" => int_src1 := reg12;
                    when "1101" => int_src1 := reg13;
                    when "1110" => int_src1 := reg14;
                    when "1111" => int_src1 := reg15;
                    when others => NULL;
                end case;

----decoding of src2 to determine register used for <src1>

                case src2 is
                    when "0000" => int_src2 := reg0;
                    when "0001" => int_src2 := reg1;
                    when "0010" => int_src2 := reg2;
                    when "0011" => int_src2 := reg3;
                    when "0100" => int_src2 := reg4;
                    when "0101" => int_src2 := reg5;
                    when "0110" => int_src2 := reg6;
                    when "0111" => int_src2 := reg7;
                    when "1000" => int_src2 := reg8;
                    when "1001" => int_src2 := reg9;
                    when "1010" => int_src2 := reg10;
                    when "1011" => int_src2 := reg11;
                    when "1100" => int_src2 := reg12;
                    when "1101" => int_src2 := reg13;
                    when "1110" => int_src2 := reg14;
                    when "1111" => int_src2 := reg15;
                    when others => NULL;
                end case;

----decoding of dest to determine register used for <src1>

                case dest is
                    when "0000" => int_dest := reg0;
                    when "0001" => int_dest := reg1;
                    when "0010" => int_dest := reg2;
                    when "0011" => int_dest := reg3;
                    when "0100" => int_dest := reg4;
                    when "0101" => int_dest := reg5;
                    when "0110" => int_dest := reg6;
                    when "0111" => int_dest := reg7;
                    when "1000" => int_dest := reg8;
                    when "1001" => int_dest := reg9;
                    when "1010" => int_dest := reg10;
                    when "1011" => int_dest := reg11;
                    when "1100" => int_dest := reg12;
                    when "1101" => int_dest := reg13;
                    when "1110" => int_dest := reg14;
                    when "1111" => int_dest := reg15;
                    when others => NULL;
                end case;

                if (int_command = LOAD) then

----default pd_data to value of data when a LOAD instruction is decoded

                    pd_data <= data;
                else 
                    pd_data <= (others => '0');
                end if;

            else
                pd_data <= (others => '0');

----default to NOP when flush is detected '1'

                int_command := NOP;
                pd_read <= '0';
            end if;

            cmd <= int_command;
            pd_src1 <= int_src1;
            pd_src2 <= int_src2;
            pd_dest <= int_dest;
        end if;
    end process;
end predecode_arch;



----this code is not good style, it will inference more registers. jxwang