pipeline_pkg.vhd

来自「vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;

package pipeline_pkg is
    type command_type is (MOVE, ADD, SUB, MUL, CJE, LOAD, READ, NOP);
    type register_type is (reg0, reg1, reg2, reg3, reg4, reg5, reg6, 
                           reg7, reg8, reg9, reg10, reg11, reg12, 
                           reg13, reg14, reg15);
    type array_size is array (0 to 15) of std_logic_vector(31 downto 0);
    constant ZERO : std_logic_vector(31 downto 0) := (others => '0');
end pipeline_pkg;