regfile_tb.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity regfile_tb_ent is
end regfile_tb_ent;

architecture regfile_tb_arch of regfile_tb_ent is
    component regfile_ent
        port (
              pd_read : in std_logic;
              pd_src1 : in register_type;
              pd_src2 : in register_type;
              clk : in std_logic;
              flush : in std_logic;
              ex_store : in std_logic;
              ex_dest : in register_type;
              ex_data : in std_logic_vector(31 downto 0);
              src1_data : out std_logic_vector(31 downto 0);
              src2_data : out std_logic_vector(31 downto 0)
             );
    end component;

    signal pd_read : std_logic;
    signal pd_src1 : register_type;
    signal pd_src2 : register_type;
    signal clk : std_logic := '0';
    signal flush : std_logic;
    signal ex_store : std_logic;
    signal ex_dest : register_type;
    signal ex_data : std_logic_vector(31 downto 0);
    signal src1_data : std_logic_vector(31 downto 0);
    signal src2_data : std_logic_vector(31 downto 0);
    
    constant CYCLE : TIME := 50 ns;

begin
    dut : regfile_ent port map(pd_read, pd_src1, pd_src2, clk, flush, ex_store, ex_dest, ex_data, src1_data, src2_data);

    clk <= not clk after CYCLE/2;

    process
    begin

----set default to 0
        flush <= '0';
        pd_read <= '0';
        pd_src1 <= reg0;
        pd_src2 <= reg0;
        ex_store <= '0';
        ex_dest <= reg0;
        ex_data <= ZERO;
        wait for CYCLE;

----load #10051, reg0;

        ex_store <= '1';
        ex_dest <= reg0;
        ex_data <= "00000000000000010000000001010001";
        wait for CYCLE;

----load #1, reg0;

        ex_store <= '1';
        ex_dest <= reg1;
        ex_data <= "00000000000000000000000000000001";
        wait for CYCLE;

----add reg0, reg1, reg2
----reading values of reg0 and reg1

        ex_store <= '0';
        pd_read <= '1';
        pd_src1 <= reg0;
        pd_src2 <= reg1;
        wait for CYCLE;

----sub reg0, reg1, reg2
----reading values of reg0 and reg1

        ex_store <= '0';
        pd_read <= '1';
        pd_src1 <= reg0;
        pd_src2 <= reg1;
        wait for CYCLE;

    end process;
end regfile_tb_arch;

configuration regfile_tb_config of regfile_tb_ent is
    for regfile_tb_arch
        for all : regfile_ent
            use entity work.regfile_ent(regfile_arch);
        end for;
    end for;
end regfile_tb_config;