predecode_tb.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity predecode_tb_ent is
end predecode_tb_ent;

architecture predecode_tb_arch of predecode_tb_ent is
    component predecode_ent
        port (clk : in std_logic;
              inst : in std_logic_vector(2 downto 0);
              src1 : in std_logic_vector(3 downto 0);
              src2 : in std_logic_vector(3 downto 0);
              dest : in std_logic_vector(3 downto 0);
              data : in std_logic_vector(31 downto 0);
              flush : in std_logic;
              cmd : out command_type;
              pd_src1 : out register_type;
              pd_src2 : out register_type;
              pd_dest : out register_type;
              pd_data : out std_logic_vector(31 downto 0);
              pd_read : out std_logic);
    end component;

    signal data : std_logic_vector(31 downto 0);
    signal src1 : std_logic_vector(3 downto 0);
    signal src2 : std_logic_vector(3 downto 0);
    signal clk : std_logic := '0';
    signal inst : std_logic_vector(2 downto 0);
    signal dest : std_logic_vector(3 downto 0);
    signal flush : std_logic;
    signal command : command_type;
    signal pd_src1 : register_type;
    signal pd_src2 : register_type;
    signal pd_dest : register_type;
    signal pd_data : std_logic_vector(31 downto 0);
    signal pd_read : std_logic;

    constant CYCLE : time := 50 ns;

begin
    dut : predecode_ent port map (clk, inst, src1, src2, dest, data, 
              flush, command, pd_src1, pd_src2, pd_dest, pd_data, pd_read);

    clk <= not clk after CYCLE/2;

    process
    begin

----default output set to 0

        src1 <= "0000";
        src2 <= "0000";
        dest <= "0000";
        data <= ZERO;
        inst <= "111";

----flush is '0', no flushing

        flush <= '0';

----load "4592fa83" into reg0 instruction

        inst <= "101";
        data <= "01000101100100101111101010000011";
        dest <= "0000";
        wait for CYCLE;

----load "00000001" into reg15 instruction

        inst <= "101";
        data <= "00000000000000000000000000000001";
        dest <= "1111";
        wait for CYCLE;

----move reg0, reg8

        inst <= "000";
        src1 <= "0000";
        dest <= "1000";
        wait for CYCLE;

----add reg0, reg15, reg1

        inst <= "001";
        src1 <= "0000";
        src2 <= "1111";
        dest <= "0001";
        wait for CYCLE;

----no operation

        inst <= "111";
        wait for CYCLE;
        inst <= "111";
        wait for CYCLE;

    end process;
end predecode_tb_arch;

configuration predecode_tb_config of predecode_tb_ent is
    for predecode_tb_arch
        for all : predecode_ent
            use entity work.predecode_ent(predecode_arch);
        end for;
    end for;
end predecode_tb_config;