decode.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity decode_ent is
    port (
          clk : in std_logic;
          cmd : in command_type;
          pd_src1 : in register_type;
          pd_src2 : in register_type;
          pd_dest : in register_type;
          pd_data : in std_logic_vector(31 downto 0);
          flush : in std_logic;
          d_cmd : out command_type;
          d_dest : out register_type;
          d_src1 : out register_type;
          d_src2 : out register_type;
          d_data : out std_logic_vector(31 downto 0)
         );
end decode_ent;

architecture decode_arch of decode_ent is
begin
    process(clk, cmd, pd_src1, pd_src2, pd_dest, flush, pd_data)
    begin
        if (clk'event and clk = '1') then 
            if (flush = '0') then
                case cmd is
                    when MOVE =>

----MOVE <src1>, <dest>, <src2> is default to reg0, d_data 
----defaulted to all zero since it is only used during LOAD

                        d_src1 <= pd_src1;
                        d_src2 <= reg0;
                        d_dest <= pd_dest;
                        d_data <= ZERO;

                    when ADD | SUB | MUL | CJE =>

----ADD <src1>, <src2>, <dest>, d_data defaulted to all zeros
----SUB <src1>, <src2>, <dest>, d_data defaulted to all zeros
----MUL <src1>, <src2>, <dest>, d_data defaulted to all zeros
----CJE <src1>, <src2>, <dest>, d_data defaulted to all zeros

                        d_src1 <= pd_src1;
                        d_src2 <= pd_src2;
                        d_dest <= pd_dest;
                        d_data <= ZERO;

                    when LOAD =>

----LOAD <value>, <dest>, d_data passes the data from predecode
----block to execute block. <src1> and <src2> are defaulted to reg0,
----they are not used in this instruction.

                        d_src1 <= reg0;
                        d_src2 <= reg0;
                        d_dest <= pd_dest;
                        d_data <= pd_data;

                    when READ =>

----READ <dest>, <src1> and <src2> default to reg0 as they are not used.
----d_data defaults to all zero.

                        d_src1 <= reg0;
                        d_src2 <= reg0;
                        d_dest <= pd_dest;
                        d_data <= ZERO;

                    when NOP =>

----no operation. all outputs to default value.

                        d_src1 <= reg0;
                        d_src2 <= reg0;
                        d_dest <= reg0;
                        d_data <= ZERO;

                    when others => NULL;
                end case;

                d_cmd <= cmd;
            else
                d_src1 <= reg0;
                d_src2 <= reg0;
                d_dest <= reg0;
                d_data <= ZERO;
                d_cmd <= NOP;
            end if;
        end if;
    end process;
end decode_arch;