execute_tb.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity execute_tb_ent is
end execute_tb_ent;

architecture execute_tb_arch of execute_tb_ent is
    component execute_ent
        port (
              d_cmd : in command_type;
              d_src1_data : in std_logic_vector(31 downto 0);
              d_src2_data : in std_logic_vector(31 downto 0);
              d_dest : in register_type;
              d_src1 : in register_type;
              d_src2 : in register_type;
              d_data : in std_logic_vector(31 downto 0);
              clk : in std_logic;
              flush : out std_logic;
              jump : out std_logic;
              ex_data : out std_logic_vector(31 downto 0);
              ex_dest : out register_type;
              ex_store : out std_logic;
              outp : out std_logic_vector(31 downto 0)
             );
    end component;

    signal d_cmd : command_type;
    signal d_src1_data : std_logic_vector(31 downto 0);
    signal d_src2_data : std_logic_vector(31 downto 0);
    signal d_dest : register_type;
    signal d_src1 : register_type;
    signal d_src2 : register_type;
    signal d_data : std_logic_vector(31 downto 0);
    signal clk : std_logic := '0';
    signal flush : std_logic;
    signal jump : std_logic;
    signal ex_data : std_logic_vector(31 downto 0);
    signal ex_dest : register_type;
    signal ex_store : std_logic;
    signal outp : std_logic_vector(31 downto 0);

    constant CYCLE : TIME := 50 ns;

begin
    dut : execute_ent port map(d_cmd, d_src1_data, d_src2_data, d_dest, d_src1, d_src2, d_data, clk, flush, jump, ex_data, ex_dest, ex_store, outp);

    clk <= not clk after CYCLE / 2;

    process
    begin
        wait for CYCLE;

----load #51, reg0

        d_cmd <= LOAD;
        d_dest <= reg0;
        d_data <= "00000000000000000000000001010001";
        wait for CYCLE;

----load #1, reg1

        d_cmd <= LOAD;
        d_dest <= reg1;
        d_data <= "00000000000000000000000000000001";
        wait for CYCLE;

----add reg0, reg1, reg2

        d_cmd <= ADD;
        d_src1 <= reg0;
        d_src2 <= reg1;
        d_dest <= reg2;
        d_src1_data <= "00000000000000000000000001010001";
        d_src2_data <= "00000000000000000000000000000001";
        wait for CYCLE;

----sub reg0, reg1, reg3

        d_cmd <= SUB;
        d_src1 <= reg0;
        d_src2 <= reg1;
        d_dest <= reg3;
        d_src1_data <= "00000000000000000000000001010001";
        d_src2_data <= "00000000000000000000000000000001";
        wait for CYCLE;

----load #1, reg4

        d_cmd <= LOAD;
        d_dest <= reg4;
        d_data <= "00000000000000000000000110000001";
        wait for CYCLE;

----mul reg0, reg4, reg5

        d_cmd <= MUL;
        d_src1 <= reg0;
        d_src2 <= reg1;
        d_dest <= reg3;
        d_src1_data <= "00000000000000000000000001010001";
        d_src2_data <= "00000000000000000000000110000001";
        wait for CYCLE;

    end process;
end execute_tb_arch;

configuration execute_tb_config of execute_tb_ent is
    for execute_tb_arch
        for all : execute_ent
            use entity work.execute_ent(execute_arch);
        end for;
    end for;
end execute_tb_config;