mcu_top_tb.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;

entity mcu_top_tb_ent is
end mcu_top_tb_ent;

architecture mcu_top_tb_arch of mcu_top_tb_ent is
    component mcu_top_ent
        port (
              clk : in std_logic;
              inst : in std_logic_vector(2 downto 0);
              src1 : in std_logic_vector(3 downto 0);
              src2 : in std_logic_vector(3 downto 0);
              dest : in std_logic_vector(3 downto 0);
              data : in std_logic_vector(31 downto 0);
              jump : out std_logic;
              outp : out std_logic_vector(31 downto 0)
             );
    end component;

    signal s_clk : std_logic := '0';
    signal s_inst : std_logic_vector(2 downto 0);
    signal s_src1 : std_logic_vector(3 downto 0);
    signal s_src2 : std_logic_vector(3 downto 0);
    signal s_dest : std_logic_vector(3 downto 0);
    signal s_data : std_logic_vector(31 downto 0);
    signal s_jump : std_logic;
    signal s_outp : std_logic_vector(31 downto 0);

    constant CYCLE : TIME := 50 ns;
    constant ZERO : std_logic_vector(31 downto 0) := 
                    "00000000000000000000000000000000";

begin
    s_clk <= not s_clk after CYCLE / 2;

    dut_mcu_top : mcu_top_ent port map (
                  clk => s_clk,
                  inst => s_inst,
                  src1 => s_src1,
                  src2 => s_src2,
                  dest => s_dest,
                  data => s_data,
                  jump => s_jump,
                  outp => s_outp);

    process
    begin

----load #51, reg0

        s_inst <= "101";
        s_src1 <= "0000";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= "00000000000000000000000001010001";
        wait for 2 * CYCLE;

----load #2, reg1

        s_inst <= "101";
        s_src1 <= "0000";
        s_src2 <= "0000";
        s_dest <= "0001";
        s_data <= "00000000000000000000000000000010";
        wait for CYCLE;

----add reg0, reg1, reg2

        s_inst <= "001";
        s_src1 <= "0000";
        s_src2 <= "0001";
        s_dest <= "0010";
        s_data <= ZERO;
        wait for CYCLE;

----sub reg0, reg1, reg3

        s_inst <= "010";
        s_src1 <= "0000";
        s_src2 <= "0001";
        s_dest <= "0011";
        s_data <= ZERO;
        wait for CYCLE;

----mul reg0, reg1, reg4

        s_inst <= "011";
        s_src1 <= "0000";
        s_src2 <= "0001";
        s_dest <= "0100";
        s_data <= ZERO;
        wait for CYCLE;

----mov reg1, reg5

        s_inst <= "000";
        s_src1 <= "0001";
        s_src2 <= "0000";
        s_dest <= "0101";
        s_data <= ZERO;
        wait for CYCLE;

----mov reg1, reg6

        s_inst <= "000";
        s_src1 <= "0001";
        s_src2 <= "0000";
        s_dest <= "0110";
        s_data <= ZERO;
        wait for CYCLE;

----cmp reg5, reg6

        s_inst <= "100";
        s_src1 <= "0101";
        s_src2 <= "0110";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----penalty 2 clocks

        wait for CYCLE;
        wait for CYCLE;

----read reg0

        s_inst <= "110";
        s_src1 <= "0000";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg1

        s_inst <= "110";
        s_src1 <= "0001";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg2

        s_inst <= "110";
        s_src1 <= "0010";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg3

        s_inst <= "110";
        s_src1 <= "0011";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg4

        s_inst <= "110";
        s_src1 <= "0100";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg5

        s_inst <= "110";
        s_src1 <= "0101";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

----read reg6

        s_inst <= "110";
        s_src1 <= "0110";
        s_src2 <= "0000";
        s_dest <= "0000";
        s_data <= ZERO;
        wait for CYCLE;

    end process;
end mcu_top_tb_arch;

configuration mcu_top_tb_config of mcu_top_tb_ent is
    for mcu_top_tb_arch
        for all : mcu_top_ent
            use entity work.mcu_top_ent(mcu_top_arch);
        end for;
    end for;
end mcu_top_tb_config;