decode_tb.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity decode_tb_ent is
end decode_tb_ent;

architecture decode_tb_arch of decode_tb_ent is
    component decode_ent
        port (clk : in std_logic;
              cmd : in command_type;
              pd_src1 : in register_type;
              pd_src2 : in register_type;
              pd_dest : in register_type;
              pd_data : in std_logic_vector(31 downto 0);
              flush : in std_logic;
              d_cmd : out command_type;
              d_dest : out register_type;
              d_src1 : out register_type;
              d_src2 : out register_type;
              d_data : out std_logic_vector(31 downto 0));
    end component;

    signal d_cmd : command_type;
    signal d_dest : register_type;
    signal d_src1 : register_type;
    signal d_src2 : register_type;
    signal pd_src1 : register_type;
    signal pd_src2 : register_type;
    signal clk : std_logic := '0';
    signal pd_dest : register_type;
    signal flush : std_logic;
    signal cmd : command_type;
    signal pd_data : std_logic_vector(31 downto 0);
    signal d_data : std_logic_vector(31 downto 0);

    constant CYCLE : TIME := 50 ns;

begin
    dut : decode_ent port map(clk, cmd, pd_src1, pd_src2, pd_dest, pd_data, flush, d_cmd, d_dest, d_src1, d_src2, d_data);

    clk <= not clk after CYCLE/2;

    process
    begin
        flush <= '0';
        wait for CYCLE;

----load #10051 reg0

        cmd <= LOAD;
        pd_dest <= reg0;
        pd_data <= "00000000000000010000000001010001";
        wait for CYCLE;

----load #1 reg1

        cmd <= LOAD;
        pd_dest <= reg1;
        pd_data <= "00000000000000000000000000000001";
        wait for CYCLE;

----add reg0, reg1, reg2

        cmd <= ADD;
        pd_src1 <= reg0;
        pd_src2 <= reg1;
        pd_dest <= reg2;
        wait for CYCLE;
        
----sub reg0, reg1, reg3

        cmd <= SUB;
        pd_src1 <= reg0;
        pd_src2 <= reg1;
        pd_dest <= reg3;
        wait for CYCLE;
    end process;
end decode_tb_arch;

configuration decode_tb_config of decode_tb_ent is
    for decode_tb_arch
        for all : decode_ent
            use entity work.decode_ent(decode_arch);
        end for;
    end for;
end decode_tb_config;