📄 mcu.dctcl
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analyze -f vhdl src/pipeline_pkg.vhd
analyze -f vhdl src/predecode.vhd
analyze -f vhdl src/decode.vhd
analyze -f vhdl src/regfile.vhd
analyze -f vhdl src/execute.vhd
analyze -f vhdl src/mcu_top.vhd
elaborate mcu_top_ent
create_clock -period 20 -waveform {0 10} -name clk [get_ports clk]
set_dont_touch_network [get_clocks clk]
set_input_transition 2.0 [remove_from_collection [all_inputs] [get_ports clk]]
set_max_transition 0.5 mcu_top_ent
set_clock_uncertainty 0.2 [get_clocks clk]
set_wire_load_model -name TSMC25_Conservative
set_wire_load_mode top
set_input_delay -max 2 -clock "clk" [all_inputs]
set_output_delay -max 2 -clock "clk" [all_outputs]
set_load 40 [all_outputs]
set_max_fanout 10 mcu_top_ent
set_scan_configuration -style multiplexed_flip_flop
set_fix_multiple_port_nets -all -buffer_constants
compile -map_effort medium
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