mcu_top.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity mcu_top_ent is
    port (
          clk : in std_logic;
          inst : in std_logic_vector(2 downto 0);
          src1 : in std_logic_vector(3 downto 0);
          src2 : in std_logic_vector(3 downto 0);
          dest : in std_logic_vector(3 downto 0);
          data : in std_logic_vector(31 downto 0);
          jump : out std_logic;
          outp : out std_logic_vector(31 downto 0)
         );
end mcu_top_ent;

architecture mcu_top_arch of mcu_top_ent is
    component execute_ent
        port (
              d_cmd : in command_type;
              d_src1_data : in std_logic_vector(31 downto 0);
              d_src2_data : in std_logic_vector(31 downto 0);
              d_dest : in register_type;
              d_src1 : in register_type;
              d_src2 : in register_type;
              d_data : in std_logic_vector(31 downto 0);
              clk : in std_logic;
              flush : out std_logic;
              jump : out std_logic;
              ex_data : out std_logic_vector(31 downto 0);
              ex_dest : out register_type;
              ex_store : out std_logic;
              outp : out std_logic_vector(31 downto 0)
             );
    end component;

    component regfile_ent 
        port (
              pd_read : in std_logic;
              pd_src1 : in register_type;
              pd_src2 : in register_type;
              clk : in std_logic;
              flush : in std_logic;
              ex_store : in std_logic;
              ex_dest : in register_type;
              ex_data : in std_logic_vector(31 downto 0);
              src1_data : out std_logic_vector(31 downto 0);
              src2_data : out std_logic_vector(31 downto 0)
             );
    end component;

    component decode_ent
        port (
              clk : in std_logic;
              cmd : in command_type;
              pd_src1 : in register_type;
              pd_src2 : in register_type;
              pd_dest : in register_type;
              pd_data : in std_logic_vector(31 downto 0);
              flush : in std_logic;
              d_cmd : out command_type;
              d_dest : out register_type;
              d_src1 : out register_type;
              d_src2 : out register_type;
              d_data : out std_logic_vector(31 downto 0)
         );
    end component;

    component predecode_ent
        port (
              clk : in std_logic;
              inst : in std_logic_vector(2 downto 0);
              src1 : in std_logic_vector(3 downto 0);
              src2 : in std_logic_vector(3 downto 0);
              dest : in std_logic_vector(3 downto 0);
              data : in std_logic_vector(31 downto 0);
              flush : in std_logic;
              cmd : out command_type;
              pd_src1 : out register_type;
              pd_src2 : out register_type;
              pd_dest : out register_type;
              pd_data : out std_logic_vector(31 downto 0);
              pd_read : out std_logic
             );
    end component;

    signal s_clk : std_logic;
    signal s_inst : std_logic_vector(2 downto 0);
    signal s_src1 : std_logic_vector(3 downto 0);
    signal s_src2 : std_logic_vector(3 downto 0);
    signal s_dest : std_logic_vector(3 downto 0);
    signal s_data : std_logic_vector(31 downto 0);
    signal s_jump : std_logic;
    signal s_outp : std_logic_vector(31 downto 0);
    signal s_flush : std_logic;
    signal s_cmd : command_type;
    signal s_pd_src1 : register_type;
    signal s_pd_src2 : register_type;
    signal s_pd_dest : register_type;
    signal s_pd_data : std_logic_vector(31 downto 0);
    signal s_ex_data : std_logic_vector(31 downto 0);
    signal s_ex_dest : register_type;
    signal s_ex_store : std_logic;
    signal s_d_cmd : command_type;
    signal s_d_src1_data : std_logic_vector(31 downto 0);
    signal s_d_src2_data : std_logic_vector(31 downto 0);
    signal s_d_dest : register_type;
    signal s_d_src1 : register_type;
    signal s_d_src2 : register_type;
    signal s_pd_read : std_logic;
    signal s_d_data : std_logic_vector(31 downto 0);
    
begin
    dut_predecode : predecode_ent port map (
                    clk => s_clk,
                    inst => s_inst,
                    src1 => s_src1,
                    src2 => s_src2,
                    dest => s_dest,
                    data => s_data,
                    flush => s_flush,
                    cmd => s_cmd,
                    pd_src1 => s_pd_src1,
                    pd_src2 => s_pd_src2,
                    pd_dest => s_pd_dest,
                    pd_data => s_pd_data,
                    pd_read => s_pd_read);

    dut_decode : decode_ent port map (
                    clk => s_clk,
                    cmd => s_cmd,
                    pd_src1 => s_pd_src1,
                    pd_src2 => s_pd_src2,
                    pd_dest => s_pd_dest,
                    pd_data => s_pd_data,
                    flush => s_flush,
                    d_cmd => s_d_cmd,
                    d_dest => s_d_dest,
                    d_src1 => s_d_src1,
                    d_src2 => s_d_src2,
                    d_data => s_d_data);

    dut_regfile : regfile_ent port map (
                    pd_read => s_pd_read,
                    pd_src1 => s_pd_src1,
                    pd_src2 => s_pd_src2,
                    clk => s_clk,
                    flush => s_flush,
                    ex_store => s_ex_store,
                    ex_dest => s_ex_dest,
                    ex_data => s_ex_data,
                    src1_data => s_d_src1_data,
                    src2_data => s_d_src2_data);

    dut_execute : execute_ent port map (
                    d_cmd => s_d_cmd,
                    d_src1_data => s_d_src1_data,
                    d_src2_data => s_d_src2_data,
                    d_dest => s_d_dest,
                    d_src1 => s_d_src1,
                    d_src2 => s_d_src2,
                    d_data => s_d_data,
                    clk => s_clk,
                    flush => s_flush,
                    jump => s_jump,
                    ex_data => s_ex_data,
                    ex_dest => s_ex_dest,
                    ex_store => s_ex_store,
                    outp => s_outp);

    s_clk <= clk;
    s_inst <= inst;
    s_src1 <= src1;
    s_src2 <= src2;
    s_dest <= dest;
    s_data <= data;
    jump <= s_jump;
    outp <= s_outp;

end mcu_top_arch;

configuration mcu_top_config of mcu_top_ent is
    for mcu_top_arch
        for all : predecode_ent
            use entity work.predecode_ent(predecode_arch);
        end for;
        for all : decode_ent
            use entity work.decode_ent(decode_arch);
        end for;
        for all : regfile_ent
            use entity work.regfile_ent(regfile_arch);
        end for;
        for all : execute_ent
            use entity work.execute_ent(execute_arch);
        end for;
    end for;
end mcu_top_config;