regfile.vhd

vhdl语言编程软件应用于学习教程。适合于初学者进行vhdl语言的学习。

library ieee;
use ieee.std_logic_1164.all;
use work.pipeline_pkg.all;

entity regfile_ent is
    port (
          pd_read : in std_logic;
          pd_src1 : in register_type;
          pd_src2 : in register_type;
          clk : in std_logic;
          flush : in std_logic;
          ex_store : in std_logic;
          ex_dest : in register_type;
          ex_data : in std_logic_vector(31 downto 0);
          src1_data : out std_logic_vector(31 downto 0);
          src2_data : out std_logic_vector(31 downto 0)
         );
end regfile_ent;

architecture regfile_arch of regfile_ent is
    signal regarray : array_size;
begin
    process(clk, flush, pd_read, pd_src1, pd_src2)
    begin
        if (clk'event and clk = '1') then
            if (flush = '0') then
                if (pd_read = '1') then
                    if (pd_src1 /= ex_dest) then

----reading contents of register indicated by pd_src1,
----register contents are driven on src1_data output

                        case pd_src1 is
                            when reg0 => src1_data <= regarray(0);
                            when reg1 => src1_data <= regarray(1);
                            when reg2 => src1_data <= regarray(2);
                            when reg3 => src1_data <= regarray(3);
                            when reg4 => src1_data <= regarray(4);
                            when reg5 => src1_data <= regarray(5);
                            when reg6 => src1_data <= regarray(6);
                            when reg7 => src1_data <= regarray(7);
                            when reg8 => src1_data <= regarray(8);
                            when reg9 => src1_data <= regarray(9);
                            when reg10 => src1_data <= regarray(10);
                            when reg11 => src1_data <= regarray(11);
                            when reg12 => src1_data <= regarray(12);
                            when reg13 => src1_data <= regarray(13);
                            when reg14 => src1_data <= regarray(14);
                            when reg15 => src1_data <= regarray(15);
                            when others => NULL;
                        end case;
                    else 
                        src1_data <= ex_data;
                    end if;  --end of pd_src1 /= ex_dest condition

                    if (pd_src2 /= ex_dest) then

----reading contents of register indicated by pd_src2,
----register contents are driven on src2_data output

                        case pd_src2 is
                            when reg0 => src2_data <= regarray(0);
                            when reg1 => src2_data <= regarray(1);
                            when reg2 => src2_data <= regarray(2);
                            when reg3 => src2_data <= regarray(3);
                            when reg4 => src2_data <= regarray(4);
                            when reg5 => src2_data <= regarray(5);
                            when reg6 => src2_data <= regarray(6);
                            when reg7 => src2_data <= regarray(7);
                            when reg8 => src2_data <= regarray(8);
                            when reg9 => src2_data <= regarray(9);
                            when reg10 => src2_data <= regarray(10);
                            when reg11 => src2_data <= regarray(11);
                            when reg12 => src2_data <= regarray(12);
                            when reg13 => src2_data <= regarray(13);
                            when reg14 => src2_data <= regarray(14);
                            when reg15 => src2_data <= regarray(15);
                            when others => NULL;
                        end case;
                    else 
                        src2_data <= ex_data;
                    end if;  --end of pd_src2 /= ex_dest condition
                end if; --end of pd_read = '1' condition

                if (ex_store = '1') then
                    case ex_dest is
                        when reg0 => regarray(0) <= ex_data;
                        when reg1 => regarray(1) <= ex_data;
                        when reg2 => regarray(2) <= ex_data;
                        when reg3 => regarray(3) <= ex_data;
                        when reg4 => regarray(4) <= ex_data;
                        when reg5 => regarray(5) <= ex_data;
                        when reg6 => regarray(6) <= ex_data;
                        when reg7 => regarray(7) <= ex_data;
                        when reg8 => regarray(8) <= ex_data;
                        when reg9 => regarray(9) <= ex_data;
                        when reg10 => regarray(10) <= ex_data;
                        when reg11 => regarray(11) <= ex_data;
                        when reg12 => regarray(12) <= ex_data;
                        when reg13 => regarray(13) <= ex_data;
                        when reg14 => regarray(14) <= ex_data;
                        when reg15 => regarray(15) <= ex_data;
                        when others => NULL;
                    end case;
                end if;  --end of ex_store = '1' condition
            else

----src1_data and src2_data default to ZERO when flushing
                src1_data <= ZERO;
                src2_data <= ZERO;
            end if;
        end if;
    end process;
end regfile_arch;