cache_config.vhd

来自「用VHDL语言实现的ARM处理器的标准内核的源代码程序」· VHDL 代码 · 共 43 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package cache_config is

-----------------------------------------------------------------------------
-- Automatically generated by vhdl/mem/cache/config.pl from of .config
-----------------------------------------------------------------------------

type cfg_repl_type is (cfg_repl_rnd, cfg_repl_lrr, cfg_repl_lru );

-- icache
constant CFG_IC_SETS     : integer range 1 to 4  := 1;  -- 1-4 sets
constant CFG_IC_SET_SZ   : integer range 1 to 64 := 1;  -- 1-64 kb
constant CFG_IC_TLINE_SZ  : integer range 2 to 8  := 4; -- 2-8 words
constant CFG_IC_DLINE_SZ  : integer range 1 to 4  := 1; -- 1-4 words
constant CFG_IC_ADDR_SZ  : integer := 32;
constant CFG_IC_LOCK  : boolean := false;
constant CFG_IC_REPL  : cfg_repl_type := cfg_repl_rnd;

-- dcache

constant CFG_DC_SETS     : integer range 1 to 4  := 1;   -- 1-4 sets
constant CFG_DC_SET_SZ   : integer range 1 to 64 := 1;   -- 1-64 kb
constant CFG_DC_TLINE_SZ  : integer range 2 to 8  := 4;  -- 2-8 words
constant CFG_DC_DLINE_SZ  : integer range 1 to 8 := 1;  -- 1-4 words
constant CFG_DC_ADDR_SZ  : integer := 32;
constant CFG_DC_LOCK  : boolean := false;
constant CFG_DC_REPL  : cfg_repl_type := cfg_repl_rnd;


-- writebuffer
constant CFG_WBBUF_SZ  : integer range 1 to 16  := 2; 

-----------------------------------------------------------------------------
-- end of automatic configuration
-----------------------------------------------------------------------------

end cache_config;