📄 armdecode.vhd
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-- DAPRAM: typ
am.DAPRAM_typ := ade_DAPRAM_simm;
if insn(ADE_DAPRAM_TYP_P) = '1' then
am.DAPRAM_typ := ade_DAPRAM_sreg;
end if;
-- DPAM and LSAM: shieft direction
am.DAPRAMxLDSTAM_sdir := ash_sdir_srrx;
case insn(ADE_DAPRAMxLDSTAM_SDIR_U downto ADE_DAPRAMxLDSTAM_SDIR_D) is
when "00" =>
am.DAPRAMxLDSTAM_sdir := ash_sdir_slsl;
if insn(ADE_DAPRAMxLDSTAM_SDIRNONE_U downto ADE_DAPRAMxLDSTAM_SDIRNONE_D) = "00000000" then
am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
end if;
when "01" => am.DAPRAMxLDSTAM_sdir := ash_sdir_slsr;
when "10" => am.DAPRAMxLDSTAM_sdir := ash_sdir_sasr;
when "11" =>
if not (insn(ADE_DAPRAMxLDSTAM_SDIRROR_U downto ADE_DAPRAMxLDSTAM_SDIRROR_D) = "00000") then
am.DAPRAMxLDSTAM_sdir := ash_sdir_sror;
end if;
when others => null;
end case;
-- DAPRAM: typ
if insn(ADE_DAPRAM_TYP) = '1' then
am.DAPRAM_typ := ade_DAPRAM_immrot;
end if;
-- LDSTAM: typ
am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
if insn(ADE_LDSTAM_TYP) = '1' then
am.LDSTAM_typ := ade_LDSTAMxLSV4AM_reg;
-- am.DAPRAMxLDSTAM_sdir := ade_snone;
end if;
-- LDSTAM and LSV4AM: preindexed / postindexed
am.LDSTAMxLSV4AM_uacc := '0';
am.LDSTAMxLSV4AM_wb := '1';
if insn(ADE_LDSTAMxLSV4AM_POS) = '1' then
am.LDSTAMxLSV4AM_pos := ade_pre;
if insn(ADE_LDSTAMxLSV4AM_WB) = '0' then
am.LDSTAMxLSV4AM_wb := '0';
end if;
else
am.LDSTAMxLSV4AM_pos := ade_post;
if insn(ADE_LDSTAMxLSV4AM_WB) = '1' then
am.LDSTAMxLSV4AM_uacc := '1';
end if;
end if;
-- LSV4AM: offset, register (not shiefted)
am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
if insn(ADE_LSV4AM_TYP) = '0' then
am.LSV4AM_typ := ade_LDSTAMxLSV4AM_reg;
end if;
end;
-- todo: remember fixing recursion bug in decgen
function ade_decode_v4(
insn_in : in std_logic_vector(31 downto 0)
) return ade_decinsn is
variable arm_nop : std_logic;
variable arm_mrs : std_logic;
variable arm_bx : std_logic;
variable arm_mul : std_logic;
variable arm_mla : std_logic;
variable arm_swp : std_logic;
variable arm_sumull : std_logic;
variable arm_sumlal : std_logic;
variable arm_strhb : std_logic;
variable arm_ldrhb : std_logic;
variable arm_and : std_logic;
variable arm_sub : std_logic;
variable arm_eor : std_logic;
variable arm_rsb : std_logic;
variable arm_add : std_logic;
variable arm_sbc : std_logic;
variable arm_adc : std_logic;
variable arm_rsc : std_logic;
variable arm_msr : std_logic;
variable arm_teq : std_logic;
variable arm_cmn : std_logic;
variable arm_tst : std_logic;
variable arm_cmp : std_logic;
variable arm_orr : std_logic;
variable arm_bic : std_logic;
variable arm_mov : std_logic;
variable arm_mvn : std_logic;
variable arm_str1 : std_logic;
variable arm_str2 : std_logic;
variable arm_str3 : std_logic;
variable arm_ldr1 : std_logic;
variable arm_undefined : std_logic;
variable arm_stm : std_logic;
variable arm_ldm : std_logic;
variable arm_b : std_logic;
variable arm_swi : std_logic;
variable arm_cdp : std_logic;
variable arm_mrc : std_logic;
variable arm_mcr : std_logic;
variable arm_stc : std_logic;
variable arm_ldc : std_logic;
variable vec_1 : std_logic_vector(1 downto 0);
variable vec_2 : std_logic_vector(2 downto 0);
variable vec_3 : std_logic_vector(4 downto 0);
variable vec_4 : std_logic_vector(21 downto 0);
variable vec_5 : std_logic_vector(12 downto 0);
variable vec_6 : std_logic_vector(18 downto 0);
variable vec_7 : std_logic_vector(4 downto 0);
variable vec_8 : std_logic_vector(0 downto 0);
variable vec_9 : std_logic_vector(0 downto 0);
variable vec_10 : std_logic_vector(4 downto 0);
variable vec_11 : std_logic_vector(0 downto 0);
variable vec_12 : std_logic_vector(2 downto 0);
variable vec_13 : std_logic_vector(0 downto 0);
variable vec_14 : std_logic_vector(0 downto 0);
variable vec_15 : std_logic_vector(0 downto 0);
variable vec_16 : std_logic_vector(0 downto 0);
variable vec_17 : std_logic_vector(6 downto 0);
variable vec_18 : std_logic_vector(0 downto 0);
variable vec_19 : std_logic_vector(0 downto 0);
variable vec_20 : std_logic_vector(0 downto 0);
variable vec_21 : std_logic_vector(0 downto 0);
variable vec_22 : std_logic_vector(0 downto 0);
variable vec_23 : std_logic_vector(0 downto 0);
variable vec_24 : std_logic_vector(7 downto 0);
variable vec_25 : std_logic_vector(0 downto 0);
variable vec_26 : std_logic_vector(1 downto 0);
variable vec_27 : std_logic_vector(0 downto 0);
variable vec_28 : std_logic_vector(0 downto 0);
variable vec_29 : std_logic_vector(0 downto 0);
variable vec_30 : std_logic_vector(0 downto 0);
variable vec_31 : std_logic_vector(0 downto 0);
variable vec_32 : std_logic_vector(0 downto 0);
variable vec_33 : std_logic_vector(0 downto 0);
variable insn_return : ade_decinsn;
variable insn : std_logic_vector(31 downto 0);
begin
insn := insn_in;
-- decoder assumes littleendian: word[3 2 1 0]
insn := insn_in;
if CFG_BO_PROC = lmd_big then
insn := insn(7 downto 0) & insn(15 downto 8) & insn(23 downto 16) & insn(31 downto 24);
end if;
insn_return := type_arm_invalid;
vec_1 := insn(3 downto 2);
vec_2 := insn(31 downto 31)&insn(28 downto 28)&insn(1 downto 1);
vec_3 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
vec_4 := insn(27 downto 16)&insn(14 downto 14)&insn(12 downto 4);
arm_nop := '0';
vec_5 := insn(27 downto 24)&insn(19 downto 16)&insn(12 downto 8);
arm_mrs := '0';
vec_6 := insn(30 downto 29)&insn(23 downto 8)&insn(0 downto 0);
arm_bx := '0';
vec_7 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
vec_8 := insn(14 downto 14);
arm_mul := '0';
vec_9 := insn(14 downto 14);
arm_mla := '0';
vec_10 := insn(19 downto 16)&insn(12 downto 12);
arm_swp := '0';
arm_sumull := '0';
arm_sumlal := '0';
vec_11 := insn(12 downto 12);
arm_strhb := '0';
arm_ldrhb := '0';
vec_12 := insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
vec_13 := insn(14 downto 14);
arm_and := '0';
arm_sub := '0';
vec_14 := insn(14 downto 14);
arm_eor := '0';
arm_rsb := '0';
vec_15 := insn(14 downto 14);
arm_add := '0';
arm_sbc := '0';
vec_16 := insn(14 downto 14);
arm_adc := '0';
arm_rsc := '0';
vec_17 := insn(23 downto 20)&insn(12 downto 12)&insn(10 downto 9);
arm_msr := '0';
vec_18 := insn(14 downto 14);
arm_teq := '0';
arm_cmn := '0';
vec_19 := insn(14 downto 14);
arm_tst := '0';
arm_cmp := '0';
vec_20 := insn(14 downto 14);
arm_orr := '0';
arm_bic := '0';
vec_21 := insn(14 downto 14);
arm_mov := '0';
arm_mvn := '0';
vec_22 := insn(12 downto 12);
vec_23 := insn(1 downto 1);
arm_str1 := '0';
vec_24 := insn(31 downto 28)&insn(19 downto 16);
arm_str2 := '0';
vec_25 := insn(28 downto 28);
arm_str3 := '0';
arm_ldr1 := '0';
vec_26 := insn(28 downto 28)&insn(1 downto 1);
arm_undefined := '0';
vec_27 := insn(1 downto 1);
vec_28 := insn(12 downto 12);
arm_stm := '0';
arm_ldm := '0';
arm_b := '0';
vec_29 := insn(1 downto 1);
vec_30 := insn(0 downto 0);
arm_swi := '0';
vec_31 := insn(28 downto 28);
arm_cdp := '0';
vec_32 := insn(12 downto 12);
arm_mrc := '0';
arm_mcr := '0';
vec_33 := insn(12 downto 12);
arm_stc := '0';
arm_ldc := '0';
case vec_1 is
when "00" =>
case vec_2 is
when "000" =>
case vec_3 is
when "00111" =>
case vec_4 is
when "0000000000000000001110" =>
arm_nop := '1';
if arm_nop = '1' then
insn_return := type_arm_nop;
end if;
when others => null;
end case;
when "00001" =>
case vec_5 is
when "0000000001111" =>
arm_mrs := '1';
if arm_mrs = '1' then
insn_return := type_arm_mrs;
end if;
when others => null;
end case;
when others => null;
end case;
when "010" =>
case vec_6 is
when "0011111111001011111" =>
arm_bx := '1';
if arm_bx = '1' then
insn_return := type_arm_bx;
end if;
when others => null;
end case;
when "110" =>
case vec_7 is
when "00000" =>
case vec_8 is
when "0" =>
arm_mul := '1';
if arm_mul = '1' then
insn_return := type_arm_mul;
end if;
when others => null;
end case;
when "00010" =>
case vec_9 is
when "0" =>
arm_mla := '1';
if arm_mla = '1' then
insn_return := type_arm_mla;
end if;
when others => null;
end case;
when "00001" =>
case vec_10 is
when "00000" =>
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