core.plg

用VHDL语言实现的ARM处理器的标准内核的源代码程序

@P:  Worst Slack : 0.905
@P:  clk - Estimated Frequency : 52.4 MHz
@P:  clk - Requested Frequency : 50.0 MHz
@P:  clk - Estimated Period : 19.095
@P:  clk - Requested Period : 20.000
@P:  clk - Slack : 0.905
@P: core Part : xcv1000efg1156-6
@P: core I/O primitives : 116
@P: core I/O Register bits : 114
@P: core Register bits (Non I/O) : 1849 (7%)
@P: core Block Rams : 6 of 96 (6%)
@P: core Total Luts : 4652 (18%)