iicrd_syn_hier_info

用FPGA实现IIC通讯的主控端

|iicrd
sda_z2_322u => iicdataout_p1_322u[0]~reg0.DATAA
sda_z2_322u => i~3579.DATAB
sda_z2_322u => i~18015.DATAC
sda_z2_322u => i~18004.DATAB
xiicask_1 => i~10078.DATAA
xiicask_1 => i~10083.DATAA
xiicask_1 => i~2762.DATAB
xiicask_1 => iiclecoun_s3_321d[0].DATAD
xiicask_1 => iiclecoun_s3_321d[1].DATAD
xiicask_1 => iiclecoun_s3_321d[2].DATAD
xiicask_1 => iiclecoun_s3_321d[3].DATAD
xiicask_1 => iiclecoun_s3_321d[4].DATAD
xiicask_1 => iiclecoun_s3_321d[5].DATAD
xiicask_1 => iiclecoun_s3_321d[6].DATAD
xiicask_1 => iiclecoun_s3_321d[7].DATAD
xiicask_1 => rtl~762.DATAD
xiicask_1 => i~19347.DATAC
xiicask_1 => iiclength_s3_321d[7]~33.DATAB
xiicask_1 => i~60.DATAA
xiicask_1 => add_73_rtl_4~3294.DATAA
xiichange_1 => i~10078.DATAB
xiichange_1 => i~2762.DATAD
xiichange_1 => rtl~58.DATAD
xiichange_1 => i~19347.DATAD
xiichange_1 => iiclength_s3_321d[7]~33.DATAD
xiichange_1 => i~60.DATAC
xiichange_1 => i~3.DATAD
clkmain1 => iicend_p1_321d~reg0.CLK
clkmain1 => iicdataout_p1_322u[7]~reg0.CLK
clkmain1 => iicdataout_p1_322u[6]~reg0.CLK
clkmain1 => iicdataout_p1_322u[5]~reg0.CLK
clkmain1 => iicdataout_p1_322u[4]~reg0.CLK
clkmain1 => iicdataout_p1_322u[3]~reg0.CLK
clkmain1 => iicdataout_p1_322u[2]~reg0.CLK
clkmain1 => iicdataout_p1_322u[1]~reg0.CLK
clkmain1 => iicdataout_p1_322u[0]~reg0.CLK
clkmain1 => scl_p1_322u~reg0.CLK
clkmain1 => temp_s0_321d[2].CLK
clkmain1 => temp_s0_321d[1].CLK
clkmain1 => temp_s0_321d[0].CLK
clkmain1 => iicwork_s1_322u.CLK
clkmain1 => temp_s0_322u[4].CLK
clkmain1 => temp_s0_322u[1].CLK
clkmain1 => temp_s0_322u[2].CLK
clkmain1 => temp_s0_322u[0].CLK
clkmain1 => temp_s0_322u[3].CLK
clkmain1 => iicask_s1_321d.CLK
clkmain1 => iiclength_s3_321d[7].CLK
clkmain1 => iiclength_s3_321d[6].CLK
clkmain1 => iiclength_s3_321d[5].CLK
clkmain1 => iiclength_s3_321d[4].CLK
clkmain1 => iiclength_s3_321d[3].CLK
clkmain1 => iiclength_s3_321d[2].CLK
clkmain1 => iiclength_s3_321d[1].CLK
clkmain1 => iiclength_s3_321d[0].CLK
clkmain1 => iiclecoun_s3_321d[0].CLK
clkmain1 => iiclecoun_s3_321d[1].CLK
clkmain1 => iiclecoun_s3_321d[2].CLK
clkmain1 => iiclecoun_s3_321d[3].CLK
clkmain1 => iiclecoun_s3_321d[4].CLK
clkmain1 => iiclecoun_s3_321d[5].CLK
clkmain1 => iiclecoun_s3_321d[6].CLK
clkmain1 => iiclecoun_s3_321d[7].CLK
clkmain1 => counter_s0_322u[0].CLK
clkmain1 => counter_s0_322u[2].CLK
clkmain1 => counter_s0_322u[1].CLK
clkmain1 => sda_z2_322u~reg0.CLK
clkmain1 => i~598.CLK
clkmain1 => iicdata_s3_322d[7].CLK
clkmain1 => iicdata_s3_322d[6].CLK
clkmain1 => iicdata_s3_322d[5].CLK
clkmain1 => iicdata_s3_322d[4].CLK
clkmain1 => iicdata_s3_322d[3].CLK
clkmain1 => iicdata_s3_322d[2].CLK
clkmain1 => iicdata_s3_322d[1].CLK
clkmain1 => iicdata_s3_322d[0].CLK
reset_1 => iicend_p1_321d~reg0.ACLR
reset_1 => scl_p1_322u~reg0.ACLR
reset_1 => temp_s0_321d[2].ACLR
reset_1 => temp_s0_321d[1].ACLR
reset_1 => temp_s0_321d[0].ACLR
reset_1 => iicwork_s1_322u.ACLR
reset_1 => temp_s0_322u[4].ACLR
reset_1 => temp_s0_322u[1].ACLR
reset_1 => temp_s0_322u[2].ACLR
reset_1 => temp_s0_322u[0].ACLR
reset_1 => temp_s0_322u[3].ACLR
reset_1 => iicdataout_p1_322u[7]~62.DATAA
reset_1 => iicask_s1_321d.ACLR
reset_1 => iiclecoun_s3_321d[0].ENA
reset_1 => iiclecoun_s3_321d[1].ENA
reset_1 => iiclecoun_s3_321d[2].ENA
reset_1 => iiclecoun_s3_321d[3].ENA
reset_1 => iiclecoun_s3_321d[4].ENA
reset_1 => iiclecoun_s3_321d[5].ENA
reset_1 => iiclecoun_s3_321d[6].ENA
reset_1 => iiclecoun_s3_321d[7].ENA
reset_1 => counter_s0_322u[0].ACLR
reset_1 => counter_s0_322u[2].ACLR
reset_1 => counter_s0_322u[1].ACLR
reset_1 => sda_z2_322u~reg0.ACLR
reset_1 => i~598.ACLR
reset_1 => iiclength_s3_321d[7]~43.DATAA
reset_1 => iicdata_s3_322d[7].ENA
reset_1 => iicdata_s3_322d[6].ENA
reset_1 => iicdata_s3_322d[5].ENA
reset_1 => iicdata_s3_322d[4].ENA
reset_1 => iicdata_s3_322d[3].ENA
reset_1 => iicdata_s3_322d[2].ENA
reset_1 => iicdata_s3_322d[1].ENA
reset_1 => iicdata_s3_322d[0]~3.DATAA
xiicdatain_3[7] => iiclength_s3_321d[7].DATAA
xiicdatain_3[7] => i~1861.DATAA
xiicdatain_3[6] => iiclength_s3_321d[6].DATAA
xiicdatain_3[6] => i~3586.DATAA
xiicdatain_3[5] => iiclength_s3_321d[5].DATAA
xiicdatain_3[5] => i~3593.DATAA
xiicdatain_3[4] => iiclength_s3_321d[4].DATAA
xiicdatain_3[4] => i~3600.DATAA
xiicdatain_3[3] => iiclength_s3_321d[3].DATAA
xiicdatain_3[3] => i~3607.DATAA
xiicdatain_3[2] => iiclength_s3_321d[2].DATAA
xiicdatain_3[2] => i~3614.DATAA
xiicdatain_3[1] => iiclength_s3_321d[1].DATAA
xiicdatain_3[1] => i~3621.DATAA
xiicdatain_3[0] => iiclength_s3_321d[0].DATAA
xiicdatain_3[0] => iicdata_s3_322d[0].DATAA
iicend_p1_321d <= iicend_p1_321d~reg0
iicdataout_p1_322u[7] <= iicdataout_p1_322u[7]~reg0
iicdataout_p1_322u[6] <= iicdataout_p1_322u[6]~reg0
iicdataout_p1_322u[5] <= iicdataout_p1_322u[5]~reg0
iicdataout_p1_322u[4] <= iicdataout_p1_322u[4]~reg0
iicdataout_p1_322u[3] <= iicdataout_p1_322u[3]~reg0
iicdataout_p1_322u[2] <= iicdataout_p1_322u[2]~reg0
iicdataout_p1_322u[1] <= iicdataout_p1_322u[1]~reg0
iicdataout_p1_322u[0] <= iicdataout_p1_322u[0]~reg0
scl_p1_322u <= scl_p1_322u~reg0
sda_z2_322u <= sda_z2_322u~reg0