iicrd.csf.msg

用FPGA实现IIC通讯的主控端

{  "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 }
{  "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.402 ns register register " "Estimated most critical path is register to register delay of 8.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iiclecoun_s3_321d\[0\] 1 REG LAB_X20_Y14 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y14; REG Node = 'iiclecoun_s3_321d\[0\]'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "" { iiclecoun_s3_321d[0] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.590 ns) 1.015 ns LessThan_112~101 2 COMB LAB_X21_Y14 " "2: + IC(0.425 ns) + CELL(0.590 ns) = 1.015 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~101'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "1.015 ns" { iiclecoun_s3_321d[0] LessThan_112~101 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 1.807 ns LessThan_112~106 3 COMB LAB_X21_Y14 " "3: + IC(0.350 ns) + CELL(0.442 ns) = 1.807 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~106'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~101 LessThan_112~106 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 2.599 ns LessThan_112~108 4 COMB LAB_X21_Y14 " "4: + IC(0.350 ns) + CELL(0.442 ns) = 2.599 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~108'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~106 LessThan_112~108 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 3.391 ns LessThan_112~113 5 COMB LAB_X21_Y14 " "5: + IC(0.350 ns) + CELL(0.442 ns) = 3.391 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~113'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~108 LessThan_112~113 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 4.183 ns LessThan_112~115 6 COMB LAB_X21_Y14 " "6: + IC(0.350 ns) + CELL(0.442 ns) = 4.183 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~115'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~113 LessThan_112~115 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 4.975 ns LessThan_112~120 7 COMB LAB_X21_Y14 " "7: + IC(0.350 ns) + CELL(0.442 ns) = 4.975 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~120'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~115 LessThan_112~120 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.442 ns) 5.767 ns LessThan_112~99 8 COMB LAB_X21_Y14 " "8: + IC(0.350 ns) + CELL(0.442 ns) = 5.767 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~99'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.792 ns" { LessThan_112~120 LessThan_112~99 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.625 ns) + CELL(0.114 ns) 6.506 ns i~18004 9 COMB LAB_X21_Y14 " "9: + IC(0.625 ns) + CELL(0.114 ns) = 6.506 ns; Loc. = LAB_X21_Y14; COMB Node = 'i~18004'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_112~99 i~18004 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.442 ns) 7.468 ns i~18032 10 COMB LAB_X22_Y14 " "10: + IC(0.520 ns) + CELL(0.442 ns) = 7.468 ns; Loc. = LAB_X22_Y14; COMB Node = 'i~18032'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.962 ns" { i~18004 i~18032 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.625 ns) + CELL(0.309 ns) 8.402 ns sda_z2_322u~reg0 11 REG LAB_X22_Y14 " "11: + IC(0.625 ns) + CELL(0.309 ns) = 8.402 ns; Loc. = LAB_X22_Y14; REG Node = 'sda_z2_322u~reg0'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.934 ns" { i~18032 sda_z2_322u~reg0 } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.107 ns " "Total cell delay = 4.107 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.295 ns " "Total interconnect delay = 4.295 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "8.402 ns" { iiclecoun_s3_321d[0] LessThan_112~101 LessThan_112~106 LessThan_112~108 LessThan_112~113 LessThan_112~115 LessThan_112~120 LessThan_112~99 i~18004 i~18032 sda_z2_322u~reg0 } "NODE_NAME" } } }  } 0 }
{  "Warning" "WDAT_PRELIMINARY_TIMING" "EP1C6Q240C8 " "Timing characteristics of device EP1C6Q240C8 are preliminary" {  } {  } 0 }
{  "Warning" "WTDB_NO_CLOCKS" "" "Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clkmain1 " "Assuming node clkmain1 is an undefined clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 6 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkmain1 register iiclecoun_s3_321d\[6\] register temp_s0_322u\[3\] 93.77 MHz 10.664 ns Internal " "Clock clkmain1 has Internal fmax of 93.77 MHz between source register iiclecoun_s3_321d\[6\] and destination register temp_s0_322u\[3\] (period= 10.664 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.071 ns + Longest register register " "+ Longest register to register delay is 5.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iiclecoun_s3_321d\[6\] 1 REG LC_X20_Y16_N5 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y16_N5; REG Node = 'iiclecoun_s3_321d\[6\]'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "" { iiclecoun_s3_321d[6] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.292 ns) 1.602 ns LessThan_264~63 2 COMB LC_X21_Y15_N6 " "2: + IC(1.310 ns) + CELL(0.292 ns) = 1.602 ns; Loc. = LC_X21_Y15_N6; COMB Node = 'LessThan_264~63'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "1.602 ns" { iiclecoun_s3_321d[6] LessThan_264~63 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.114 ns) 2.165 ns LessThan_264~58 3 COMB LC_X21_Y15_N0 " "3: + IC(0.449 ns) + CELL(0.114 ns) = 2.165 ns; Loc. = LC_X21_Y15_N0; COMB Node = 'LessThan_264~58'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.563 ns" { LessThan_264~63 LessThan_264~58 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.114 ns) 2.718 ns i~19333 4 COMB LC_X21_Y15_N9 " "4: + IC(0.439 ns) + CELL(0.114 ns) = 2.718 ns; Loc. = LC_X21_Y15_N9; COMB Node = 'i~19333'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.553 ns" { LessThan_264~58 i~19333 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.292 ns) 3.488 ns i~2390 5 COMB LC_X21_Y15_N2 " "5: + IC(0.478 ns) + CELL(0.292 ns) = 3.488 ns; Loc. = LC_X21_Y15_N2; COMB Node = 'i~2390'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "0.770 ns" { i~19333 i~2390 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.309 ns) 5.071 ns temp_s0_322u\[3\] 6 REG LC_X21_Y16_N4 " "6: + IC(1.274 ns) + CELL(0.309 ns) = 5.071 ns; Loc. = LC_X21_Y16_N4; REG Node = 'temp_s0_322u\[3\]'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "1.583 ns" { i~2390 temp_s0_322u[3] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.121 ns " "Total cell delay = 1.121 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.950 ns " "Total interconnect delay = 3.950 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "5.071 ns" { iiclecoun_s3_321d[6] LessThan_264~63 LessThan_264~58 i~19333 i~2390 temp_s0_322u[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "- Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkmain1 destination 2.806 ns + Shortest register " "+ Shortest clock path from clock clkmain1 to destination register is 2.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.328 ns) 1.328 ns clkmain1 1 CLK Pin_29 " "1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "" { clkmain1 } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.711 ns) 2.806 ns temp_s0_322u\[3\] 2 REG LC_X21_Y16_N4 " "2: + IC(0.767 ns) + CELL(0.711 ns) = 2.806 ns; Loc. = LC_X21_Y16_N4; REG Node = 'temp_s0_322u\[3\]'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "1.478 ns" { clkmain1 temp_s0_322u[3] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.039 ns " "Total cell delay = 2.039 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.767 ns " "Total interconnect delay = 0.767 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 temp_s0_322u[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkmain1 source 2.806 ns - Longest register " "- Longest clock path from clock clkmain1 to source register is 2.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.328 ns) 1.328 ns clkmain1 1 CLK Pin_29 " "1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "" { clkmain1 } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.711 ns) 2.806 ns iiclecoun_s3_321d\[6\] 2 REG LC_X20_Y16_N5 " "2: + IC(0.767 ns) + CELL(0.711 ns) = 2.806 ns; Loc. = LC_X20_Y16_N5; REG Node = 'iiclecoun_s3_321d\[6\]'" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "1.478 ns" { clkmain1 iiclecoun_s3_321d[6] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.039 ns " "Total cell delay = 2.039 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.767 ns " "Total interconnect delay = 0.767 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 iiclecoun_s3_321d[6] } "NODE_NAME" } } }  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 temp_s0_322u[3] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 iiclecoun_s3_321d[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "+ Micro clock to output delay of source is 0.224 ns" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "+ Micro setup delay of destination is 0.037 ns" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } }  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "5.071 ns" { iiclecoun_s3_321d[6] LessThan_264~63 LessThan_264~58 i~19333 i~2390 temp_s0_322u[3] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 temp_s0_322u[3] } "NODE_NAME" } } } { "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd_Administrator_V1_cmp.qrpt" Compiler "iicrd" "Administrator" "V1" "D:\\all_work\\standard\\iicmainrd_32\\db\\iicrd.quartus_db" { Floorplan "" "" "2.806 ns" { clkmain1 clkmain1~out0 iiclecoun_s3_321d[6] } "NODE_NAME" } } }  } 0 }
{  "Info" "IDBC_ERROR_COUNT" "0 2 s s Full compilation iicrd successful was " "Design iicrd: Full compilation was successful. 0 errors, 2 warnings" {  } {  } 2 }