iicrd.csf.msg

用FPGA实现IIC通讯的主控端

{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd 2 1 " "Found 2 design units and 1 entities in source file D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 iicrd-behav " "Found design unit 1: iicrd-behav" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "iicrd-behav" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 19 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 iicrd " "Found entity 1: iicrd" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "iicrd" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 4 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power up high" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 11 -1 0 } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 14 -1 0 } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 261 -1 0 } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } } { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 15 -1 0 } }  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "205 " "Implemented 205 device resources" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "182 " "Implemented 182 logic cells" {  } {  } 0}  } {  } 0 }
{  "Info" "IMPP_MPP_USER_DEVICE" "iicrd EP1C6Q240C8 " "Selected device EP1C6Q240C8 for design iicrd" {  } {  } 0 }
{  "Info" "IFITCC_FITCC_SIGNALPROBE_SMART_COMPILATION_OFF" "" "Smart compilation specified to OFF -- SignalProbe information will not be saved" {  } {  } 0 }
{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkmain1 Global clock in Pin 29 " "Automatically promoted signal clkmain1 to use Global clock in Pin 29" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 6 -1 0 } }  } 0 }
{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset_1 Global clock in Pin 28 " "Automatically promoted some destinations of signal reset_1 to use Global clock in Pin 28" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iicdataout_p1_322u\[7\]~62 " "Destination iicdataout_p1_322u\[7\]~62 may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[0\] " "Destination iiclecoun_s3_321d\[0\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[1\] " "Destination iiclecoun_s3_321d\[1\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[2\] " "Destination iiclecoun_s3_321d\[2\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[3\] " "Destination iiclecoun_s3_321d\[3\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[4\] " "Destination iiclecoun_s3_321d\[4\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[5\] " "Destination iiclecoun_s3_321d\[5\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[6\] " "Destination iiclecoun_s3_321d\[6\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclecoun_s3_321d\[7\] " "Destination iiclecoun_s3_321d\[7\] may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "iiclength_s3_321d\[7\]~43 " "Destination iiclength_s3_321d\[7\]~43 may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 117 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Limited to 10 non-global destinations" {  } {  } 0}  } { { "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" "" "" { Text "D:\\all_work\\standard\\iicmainrd_32\\iicrd.vhd" 5 -1 0 } }  } 0 }