iicrd.csf.rpt

用FPGA实现IIC通讯的主控端

+--------------------------+---------------+---------+----------------------------+--------+----------------------+
| clkmain1                 | 29            | 49      | Clock                      | yes    | Global clock         |
| iicdata_s3_322d[0]~3     | LC_X23_Y17_N1 | 1       | Clock enable               | no     | --                   |
| iicdataout_p1_322u[7]~62 | LC_X23_Y18_N6 | 8       | Clock enable               | no     | --                   |
| iiclength_s3_321d[7]~43  | LC_X21_Y14_N8 | 8       | Clock enable               | no     | --                   |
| i~598                    | LC_X21_Y15_N8 | 1       | Output enable              | no     | --                   |
| reset_1                  | 28            | 35      | Async. clear, Clock enable | yes    | Global clock         |
+--------------------------+---------------+---------+----------------------------+--------+----------------------+

+-----------------------------------------------------------------------------+
| Global & Other Fast Signals                                                 |
+-----------------------------------------------------------------------------+
+----------+----------+---------+----------------------+
| Name     | Location | Fan-Out | Global Resource Used |
+----------+----------+---------+----------------------+
| clkmain1 | 29       | 49      | Global clock         |
| reset_1  | 28       | 35      | Global clock         |
+----------+----------+---------+----------------------+

+-----------------------------------------------------------------------------+
| Non-Global High Fan-Out Signals                                             |
+-----------------------------------------------------------------------------+
+--------------------------+---------+
| Name                     | Fan-Out |
+--------------------------+---------+
| temp_s0_322u[2]          | 26      |
| temp_s0_322u[3]          | 24      |
| temp_s0_322u[4]          | 23      |
| temp_s0_322u[1]          | 21      |
| temp_s0_322u[0]          | 19      |
| i~19322                  | 18      |
| reduce_nor_254           | 18      |
| temp_s0_321d[1]          | 18      |
| temp_s0_321d[0]          | 18      |
| temp_s0_321d[2]          | 18      |
| xiicask_1                | 16      |
| i~2640                   | 15      |
| iicwork_s1_322u          | 14      |
| i~19582                  | 13      |
| iicdata_s3_322d[0]~25    | 13      |
| i~3                      | 9       |
| reduce_nor_127_rtl_0~0   | 9       |
| reduce_nor_127_rtl_0~123 | 9       |
| iicask_s1_321d           | 9       |
| add_73_rtl_4~3294        | 8       |
| iiclength_s3_321d[7]~43  | 8       |
| iicdataout_p1_322u[7]~62 | 8       |
| xiichange_1              | 7       |
| counter_s0_322u[0]       | 6       |
| counter_s0_322u[1]       | 5       |
| iiclecoun_s3_321d[1]     | 5       |
| iiclecoun_s3_321d[0]     | 5       |
| scl_p1_322u~reg0         | 5       |
| sda_z2_322u              | 4       |
| counter_s0_322u[2]       | 4       |
| iiclecoun_s3_321d[7]     | 4       |
| iiclecoun_s3_321d[6]     | 4       |
| iiclecoun_s3_321d[5]     | 4       |
| iiclecoun_s3_321d[4]     | 4       |
| iiclecoun_s3_321d[3]     | 4       |
| iiclecoun_s3_321d[2]     | 4       |
| reduce_nor_254~1         | 4       |
| add_73~4                 | 4       |
| iicdata_s3_322d[1]       | 3       |
| iicdata_s3_322d[2]       | 3       |
| iicdata_s3_322d[3]       | 3       |
| iicdata_s3_322d[4]       | 3       |
| iicdata_s3_322d[5]       | 3       |
| iicdata_s3_322d[6]       | 3       |
| reduce_nor_446           | 3       |
| iicdata_s3_322d[7]       | 3       |
| i~19345                  | 3       |
| i~19504                  | 3       |
| i~19326                  | 3       |
| i~19324                  | 3       |
+--------------------------+---------+

+-----------------------------------------------------------------------------+
| Output Pin Load For Reported TCO                                            |
+-----------------------------------------------------------------------------+
+---------------------+-------+------------------------------------+
| I/O Standard        | Load  | Termination Resistance             |
+---------------------+-------+------------------------------------+
| LVTTL               | 10 pF | Not Available                      |
| LVCMOS              | 10 pF | Not Available                      |
| 2.5 V               | 10 pF | Not Available                      |
| 1.8 V               | 10 pF | Not Available                      |
| 1.5 V               | 10 pF | Not Available                      |
| SSTL-3 Class I      | 30 pF | 50 Ohm (Parallel), 25 Ohm (Serial) |
| SSTL-3 Class II     | 30 pF | 25 Ohm (Parallel), 25 Ohm (Serial) |
| SSTL-2 Class I      | 30 pF | 50 Ohm (Parallel), 25 Ohm (Serial) |
| SSTL-2 Class II     | 30 pF | 25 Ohm (Parallel), 25 Ohm (Serial) |
| LVDS                | 4 pF  | 100 Ohm                            |
| Differential SSTL-2 | 30 pF | (See SSTL-2)                       |
| 3.3-V PCI           | 10 pF | 25 Ohm                             |
+---------------------+-------+------------------------------------+

+-----------------------------------------------------------------------------+
| Interconnect Usage Summary                                                  |
+-----------------------------------------------------------------------------+
+----------------------------+------------------------+
| Interconnect Resource Type | Usage                  |
+----------------------------+------------------------+
| C4s                        | 151 / 16,320 ( < 1 % ) |
| Direct links               | 31 / 22,328 ( < 1 % )  |
| Global clocks              | 2 / 8 ( 25 % )         |
| LAB clocks                 | 12 / 240 ( 5 % )       |
| LUT chains                 | 34 / 5,382 ( < 1 % )   |
| Local interconnects        | 261 / 22,328 ( 1 % )   |
| M4K buffers                | 0 / 720 ( 0 % )        |
| R4s                        | 64 / 14,640 ( < 1 % )  |
+----------------------------+------------------------+

+-----------------------------------------------------------------------------+
| LAB Logic Elements                                                          |
+-----------------------------------------------------------------------------+
+--------------------------------------------+------------------------------+
| Number of Logic Elements  (Average = 7.91) | Number of LABs  (Total = 22) |
+--------------------------------------------+------------------------------+
| 1                                          | 2                            |
| 2                                          | 0                            |
| 3                                          | 1                            |
| 4                                          | 1                            |
| 5                                          | 2                            |
| 6                                          | 0                            |
| 7                                          | 0                            |
| 8                                          | 2                            |
| 9                                          | 1                            |
| 10                                         | 13                           |
+--------------------------------------------+------------------------------+

+-----------------------------------------------------------------------------+
| LAB-wide Signals                                                            |
+-----------------------------------------------------------------------------+
+------------------------------------+------------------------------+
| LAB-wide Signals  (Average = 1.77) | Number of LABs  (Total = 22) |
+------------------------------------+------------------------------+
| 1 Async. clear                     | 13                           |
| 1 Clock                            | 20                           |
| 1 Clock enable                     | 6                            |
+------------------------------------+------------------------------+

+-----------------------------------------------------------------------------+
| LAB Signals Sourced                                                         |
+-----------------------------------------------------------------------------+
+---------------------------------------------+------------------------------+
| Number of Signals Sourced  (Average = 7.91) | Number of LABs  (Total = 22) |
+---------------------------------------------+------------------------------+
| 0                                           | 0                            |
| 1                                           | 2                            |
| 2                                           | 0                            |
| 3                                           | 1                            |
| 4                                           | 1                            |
| 5                                           | 2                            |
| 6                                           | 0                            |
| 7                                           | 0                            |
| 8                                           | 2                            |
| 9                                           | 1                            |
| 10                                          | 13                           |
+---------------------------------------------+------------------------------+

+----------------