iicrd.csf.rpt

用FPGA实现IIC通讯的主控端

  Info: 3: + IC(0.350 ns) + CELL(0.442 ns) = 1.807 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~106'
  Info: 4: + IC(0.350 ns) + CELL(0.442 ns) = 2.599 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~108'
  Info: 5: + IC(0.350 ns) + CELL(0.442 ns) = 3.391 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~113'
  Info: 6: + IC(0.350 ns) + CELL(0.442 ns) = 4.183 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~115'
  Info: 7: + IC(0.350 ns) + CELL(0.442 ns) = 4.975 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~120'
  Info: 8: + IC(0.350 ns) + CELL(0.442 ns) = 5.767 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~99'
  Info: 9: + IC(0.625 ns) + CELL(0.114 ns) = 6.506 ns; Loc. = LAB_X21_Y14; COMB Node = 'i~18004'
  Info: 10: + IC(0.520 ns) + CELL(0.442 ns) = 7.468 ns; Loc. = LAB_X22_Y14; COMB Node = 'i~18032'
  Info: 11: + IC(0.625 ns) + CELL(0.309 ns) = 8.402 ns; Loc. = LAB_X22_Y14; REG Node = 'sda_z2_322u~reg0'
  Info: Total cell delay = 4.107 ns
  Info: Total interconnect delay = 4.295 ns
Warning: Timing characteristics of device EP1C6Q240C8 are preliminary
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node clkmain1 is an undefined clock
Info: Clock clkmain1 has Internal fmax of 93.77 MHz between source register iiclecoun_s3_321d[6] and destination register temp_s0_322u[3] (period= 10.664 ns)
  Info: + Longest register to register delay is 5.071 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y16_N5; REG Node = 'iiclecoun_s3_321d[6]'
    Info: 2: + IC(1.310 ns) + CELL(0.292 ns) = 1.602 ns; Loc. = LC_X21_Y15_N6; COMB Node = 'LessThan_264~63'
    Info: 3: + IC(0.449 ns) + CELL(0.114 ns) = 2.165 ns; Loc. = LC_X21_Y15_N0; COMB Node = 'LessThan_264~58'
    Info: 4: + IC(0.439 ns) + CELL(0.114 ns) = 2.718 ns; Loc. = LC_X21_Y15_N9; COMB Node = 'i~19333'
    Info: 5: + IC(0.478 ns) + CELL(0.292 ns) = 3.488 ns; Loc. = LC_X21_Y15_N2; COMB Node = 'i~2390'
    Info: 6: + IC(1.274 ns) + CELL(0.309 ns) = 5.071 ns; Loc. = LC_X21_Y16_N4; REG Node = 'temp_s0_322u[3]'
    Info: Total cell delay = 1.121 ns
    Info: Total interconnect delay = 3.950 ns
  Info: - Smallest clock skew is 0.000 ns
    Info: + Shortest clock path from clock clkmain1 to destination register is 2.806 ns
      Info: 1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'
      Info: 2: + IC(0.767 ns) + CELL(0.711 ns) = 2.806 ns; Loc. = LC_X21_Y16_N4; REG Node = 'temp_s0_322u[3]'
      Info: Total cell delay = 2.039 ns
      Info: Total interconnect delay = 0.767 ns
    Info: - Longest clock path from clock clkmain1 to source register is 2.806 ns
      Info: 1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'
      Info: 2: + IC(0.767 ns) + CELL(0.711 ns) = 2.806 ns; Loc. = LC_X20_Y16_N5; REG Node = 'iiclecoun_s3_321d[6]'
      Info: Total cell delay = 2.039 ns
      Info: Total interconnect delay = 0.767 ns
  Info: + Micro clock to output delay of source is 0.224 ns
  Info: + Micro setup delay of destination is 0.037 ns
  Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two

+-----------------------------------------------------------------------------+
| Hierarchy                                                                   |
+-----------------------------------------------------------------------------+
Hierarchy
  iicrd

+-----------------------------------------------------------------------------+
| Logic Options                                                               |
+-----------------------------------------------------------------------------+
+-----------------------------------+-------+
| Name                              | Value |
+-----------------------------------+-------+
| Optimization Technique -- Cyclone | Area  |
| Power-Up Don't Care               | On    |
+-----------------------------------+-------+

+-----------------------------------------------------------------------------+
| Resource Utilization by Entity                                              |
+-----------------------------------------------------------------------------+
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+
| Compilation Hierarchy Node | Logic Cells | Registers | Memory Bits | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name |
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+
| |iicrd                     | 182 (182)   | 49        | 0           | 0            | 0       | 0         | 0         | 23   | 0            | 133 (133)    | 17 (17)           | 32 (32)          | |iicrd              |
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+

+-----------------------------------------------------------------------------+
| Device Options                                                              |
+-----------------------------------------------------------------------------+
+------------------------------------------------------------------+--------------------------+
| Option                                                           | Setting                  |
+------------------------------------------------------------------+--------------------------+
| Auto-restart configuration after error                           | Off                      |
| Release clears before tri-states                                 | Off                      |
| Enable user-supplied start-up clock (CLKUSR)                     | Off                      |
| Enable device-wide reset (DEV_CLRn)                              | Off                      |
| Enable device-wide output enable (DEV_OE)                        | Off                      |
| Enable INIT_DONE output                                          | Off                      |
| Auto-increment JTAG user code for multiple configuration devices | On                       |
| Disable CONF_DONE and nSTATUS pull-ups on configuration device   | Off                      |
| Generate compressed bitstreams                                   | Off                      |
| Generate Tabular Text File (.ttf)                                | Off                      |
| Generate Raw Binary File (.rbf)                                  | Off                      |
| Generate Hexadecimal Output File (.hexout)                       | Off                      |
| Configuration scheme                                             | Passive Serial           |
| Hexadecimal Output File count direction                          | Up                       |
| Hexadecimal Output File start address                            | 0                        |
| Reserve all unused pins                                          | As output driving ground |
| Configuration device                                             | EPC2                     |
| Base pin-out file on sameframe device                            | Off                      |
| Auto user code                                                   | Off                      |
| Configuration device auto user code                              | Off                      |
| JTAG user code for target device                                 | 0XFFFFFFFF               |
| JTAG user code for configuration device                          | 0XFFFFFFFF               |
+------------------------------------------------------------------+--------------------------+

+-----------------------------------------------------------------------------+
| Equations                                                                   |
+-----------------------------------------------------------------------------+
The equations can be found in D:\all_work\standard\iicmainrd_32\iicrd.eqn.htm.

+-----------------------------------------------------------------------------+
| Floorplan View                                                              |
+-----------------------------------------------------------------------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.

+-----------------------------------------------------------------------------+
| Pin-Out File                                                                |
+-----------------------------------------------------------------------------+
The pin-out file can be found in D:\all_work\standard\iicmainrd_32\iicrd.pin.

+-----------------------------------------------------------------------------+
| Resource Usage Summary                                                      |
+-----------------------------------------------------------------------------+
+----------------------------+----------------------+
| Resource                   | Usage                |
+----------------------------+----------------------+
| Logic cells                | 174 / 5,980 ( 2 % )  |
| Registers                  | 49 / 6,535 ( < 1 % ) |
| User inserted logic cells  | 0                    |
| I/O pins                   | 23 / 185 ( 12 % )    |
| Clock pins                 | 2                    |
| Dedicated input pins       | 0                    |
| Global signals             | 2                    |
| M4Ks                       | 0 / 20 ( 0 % )       |
| Total memory bits          | 0 / 92,160 ( 0 % )   |
| Total RAM block bits       | 0 / 92,160 ( 0 % )   |
| PLLs                       | 0 / 2 ( 0 % )        |
| Global clocks              | 2 / 8 ( 25 % )       |
| Maximum fan-out node       | clkmain1             |
| Maximum fan-out            | 49                   |
| Total fan-out              | 703                  |
| Average fan-out            | 3.57                 |
+----------------------------+----------------------+

+-----------------------------------------------------------------------------+
| Resource Utilization by Entity                                              |
+-----------------------------------------------------------------------------+
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+
| Compilation Hierarchy Node | Logic Cells | Registers | Memory Bits | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name |
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+
| |iicrd                     | 174 (174)   | 49        | 0           | 0            | 0       | 0         | 0         | 23   | 0            | 125 (125)    | 9 (9)             | 40 (40)          | |iicrd              |
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+

+-----------------------------------------------------------------------------+
| Input Pins                                                                  |
+-----------------------------------------------------------------------------+
+-----------------+-------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+
| Name            | Pin # | X coordinate | Y coordinate | Cell number | Combinational Fan-Out | Registered Fan-Out | Global | Input Register | Power Up High | PCI I/O Enabled | Bus Hold | Weak Pull Up | I/O Standard | Termination |
+-----------------+-------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+
| clkmain1        | 29    | 0            | 11           | 0           | 49                    | 0                  | yes    | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| reset_1         | 28    | 0            | 12           | 2           | 35                    | 0                  | yes    | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicask_1       | 207   | 20           | 21           | 1           | 16                    | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[0] | 201   | 24           | 21           | 1           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[1] | 200   | 24           | 21           | 0           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[2] | 202   | 24           | 21           | 2           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[3] | 213   | 16           | 21           | 0           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[4] | 208   | 20           | 21           | 2           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[5] | 167   | 35           | 16           | 0           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[6] | 214   | 16           | 21           | 1           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiicdatain_3[7] | 205   | 22           | 21           | 2           | 2                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
| xiichange_1     | 206   | 20           | 21           | 0           | 7                     | 0                  | no     | no             | no            | no              | no       | Off          | LVTTL        | Off         |
+-----------------+-------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+