iicrd.csf.rpt

用FPGA实现IIC通讯的主控端

iicrd - Quartus II Compilation Report File
-------------------------------------------------------------------------------

+----------------------------------------------------------------------------+
| Report Information                                                         |
+--------------------+-------------------------------------------------------+
| Project            | D:\all_work\standard\iicmainrd_32/                    |
| Compiler Settings  | iicrd                                                 |
| Quartus II Version | 2.2 Build 191 03/31/2003 SP 2 SJ Full Version         |
+--------------------+-------------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "iicrd" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Logic Options
            Synthesis Section
                Resource Utilization by Entity
            Device Options
            Equations
            Floorplan View
            Pin-Out File
            Resource Section
                Resource Usage Summary
                Resource Utilization by Entity
                Input Pins
                Output Pins
                Bidir Pins
                Delay Chain Summary
                I/O Bank Usage
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Non-Global High Fan-Out Signals
                Output Pin Load For Reported TCO
                LAB and Routing Section
                    Interconnect Usage Summary
                    LAB Logic Elements
                    LAB-wide Signals
                    LAB Signals Sourced
                    LAB Signals Sourced Out
                    LAB Distinct Inputs
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
| Legal Notice                                                                |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
| General Settings                                                            |
+-----------------------------------------------------------------------------+
+-------------------+---------------------+
| Option            | Setting             |
+-------------------+---------------------+
| Start date & time | 03/06/2004 11:22:11 |
| Main task         | Compilation         |
| Settings name     | iicrd               |
+-------------------+---------------------+

+-----------------------------------------------------------------------------+
| Summary                                                                     |
+-----------------------------------------------------------------------------+
+-------------------------------------+-----------------------------------------------+
| Processing status                   | Fitting Successful - Sat Mar 06 11:22:43 2004 |
| Timing requirements/analysis status | No requirements                               |
| Chip name                           | iicrd                                         |
| Device for compilation              | EP1C6Q240C8                                   |
| Total logic elements                | 174 / 5,980 ( 2 % )                           |
| Total pins                          | 23 / 185 ( 12 % )                             |
| Total memory bits                   | 0 / 92,160 ( 0 % )                            |
| Total PLLs                          | 0 / 2 ( 0 % )                                 |
| Device for timing analysis          | EP1C6Q240C8                                   |
+-------------------------------------+-----------------------------------------------+

+-----------------------------------------------------------------------------+
| Compiler Settings                                                           |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------+--------------------+
| Option                                                   | Setting            |
+----------------------------------------------------------+--------------------+
| Chip name                                                | iicrd              |
| Family name                                              | Cyclone            |
| Focus entity name                                        | |iicrd             |
| Device                                                   | EP1C6Q240C8        |
| Disk space/compilation speed tradeoff                    | Normal             |
| Preserve fewer node names                                | On                 |
| Optimize timing                                          | Normal Compilation |
| Optimize IOC register placement for timing               | On                 |
| Fast Fit compilation                                     | Off                |
| Perform WYSIWYG primitive resynthesis                    | Off                |
| Perform gate-level register retiming                     | Off                |
| Use Fitter timing information during synthesis           | Off                |
| Duplicate logic elements during fitting                  | Off                |
| Duplicate logic elements/resythesize LUTs during fitting | Off                |
| SignalProbe compilation                                  | Off                |
| Generate compressed bitstreams                           | Off                |
+----------------------------------------------------------+--------------------+

+-----------------------------------------------------------------------------+
| Messages                                                                    |
+-----------------------------------------------------------------------------+
Info: Found 2 design units and 1 entities in source file D:\all_work\standard\iicmainrd_32\iicrd.vhd
  Info: Found design unit 1: iicrd-behav
  Info: Found entity 1: iicrd
Info: Registers with preset signals will power up high
Info: Implemented 205 device resources
  Info: Implemented 12 input pins
  Info: Implemented 10 output pins
  Info: Implemented 1 bidirectional pins
  Info: Implemented 182 logic cells
Info: Selected device EP1C6Q240C8 for design iicrd
Info: Smart compilation specified to OFF -- SignalProbe information will not be saved
Info: Automatically promoted signal clkmain1 to use Global clock in Pin 29
Info: Automatically promoted some destinations of signal reset_1 to use Global clock in Pin 28
  Info: Destination iicdataout_p1_322u[7]~62 may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[0] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[1] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[2] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[3] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[4] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[5] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[6] may be non-global or may not use global clock
  Info: Destination iiclecoun_s3_321d[7] may be non-global or may not use global clock
  Info: Destination iiclength_s3_321d[7]~43 may be non-global or may not use global clock
  Info: Limited to 10 non-global destinations
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 8.402 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y14; REG Node = 'iiclecoun_s3_321d[0]'
  Info: 2: + IC(0.425 ns) + CELL(0.590 ns) = 1.015 ns; Loc. = LAB_X21_Y14; COMB Node = 'LessThan_112~101'