sdram64m16.ssf.rpt

用FPGA实现SDRAM的操作

sdram64m16 - Quartus II Simulation Report File
-------------------------------------------------------------------------------

+------------------------------------------------------------------------------------+
| Report Information                                                                 |
+--------------------+---------------------------------------------------------------+
| Project            | D:\all_work\standard\sdram4m16_L2_42/                         |
| Simulator Settings | sdram64m16                                                    |
| Quartus II Version | 2.2 Build 191 03/31/2003 SP 2 SJ Full Version                 |
+--------------------+---------------------------------------------------------------+

Table of Contents
    Simulator Report
        Legal Notice
        Project Settings
            General Settings
        Results for "sdram64m16" Simulator Settings
            Summary
            Simulator Settings
            Simulation Waveforms
            Messages
            Processing Time

+-----------------------------------------------------------------------------+
| Legal Notice                                                                |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
| General Settings                                                            |
+-----------------------------------------------------------------------------+
+-------------------+---------------------+
| Option            | Setting             |
+-------------------+---------------------+
| Start date & time | 03/26/2004 14:11:27 |
| Main task         | Simulation          |
| Settings name     | sdram64m16          |
| Simulation mode   | Timing              |
| Compiler Settings | sdram64m16          |
+-------------------+---------------------+

+-----------------------------------------------------------------------------+
| Summary                                                                     |
+-----------------------------------------------------------------------------+
+-----------------------+--------------+
| Option                | Setting      |
+-----------------------+--------------+
| Simulation Start Time | 0 ps         |
| Simulation End Time   | 1.0 ms       |
| Simulation Coverage   |      69.14 % |
| Number of transitions | 2938901      |
+-----------------------+--------------+

+-----------------------------------------------------------------------------+
| Simulator Settings                                                          |
+-----------------------------------------------------------------------------+
+-------------------------------------------------------+------------+
| Option                                                | Setting    |
+-------------------------------------------------------+------------+
| Simulator settings name                               | sdram64m16 |
| Simulation mode                                       | Timing     |
| Start time                                            | 0ns        |
| Add pins automatically to simulation output waveforms | On         |
| Check outputs                                         | Off        |
| Report simulation coverage                            | On         |
| Detect setup and hold time violations                 | Off        |
| Detect glitches                                       | Off        |
| Estimate power consumption                            | Off        |
+-------------------------------------------------------+------------+

+-----------------------------------------------------------------------------+
| Simulation Waveforms                                                        |
+-----------------------------------------------------------------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.

+-----------------------------------------------------------------------------+
| Messages                                                                    |
+-----------------------------------------------------------------------------+
Warning: Ignored node in vector source file. Can't find corresponding node name temp_s0_402d[2] in design.
Warning: Compiler synthesized away node temp_s0_403d[9]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[8]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[7]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[6]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[5]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[4]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[3]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[2]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[1]. Ignored vector source file node.
Warning: Compiler synthesized away node temp_s0_403d[0]. Ignored vector source file node.

+-----------------------------------------------------------------------------+
| Processing Time                                                             |
+-----------------------------------------------------------------------------+
+-----------------+--------------+
| Module Name     | Elapsed Time |
+-----------------+--------------+
| Netlist Builder | 00:00:00     |
| Simulator       | 00:03:31     |
+-----------------+--------------+