sdram64m16.csf.msg

用FPGA实现SDRAM的操作

{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkmain1 Global clock in Pin 29 " "Automatically promoted some destinations of signal clkmain1 to use Global clock in Pin 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sdramclk " "Destination sdramclk may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 12 -1 0 } }  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 6 -1 0 } }  } 0 }
{  "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset_1 Global clock in Pin 28 " "Automatically promoted some destinations of signal reset_1 to use Global clock in Pin 28" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "addr_p3_402d\[7\]~4 " "Destination addr_p3_402d\[7\]~4 may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 17 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "addr_p3_402d\[7\]~64 " "Destination addr_p3_402d\[7\]~64 may be non-global or may not use global clock" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 17 -1 0 } }  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 5 -1 0 } }  } 0 }
{  "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 }
{  "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.538 ns register register " "Estimated most critical path is register to register delay of 9.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns length_s0_402d\[0\] 1 REG LAB_X27_Y14 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y14; REG Node = 'length_s0_402d\[0\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "" { length_s0_402d[0] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.447 ns) + CELL(0.292 ns) 0.739 ns LessThan_469~97 2 COMB LAB_X27_Y14 " "2: + IC(0.447 ns) + CELL(0.292 ns) = 0.739 ns; Loc. = LAB_X27_Y14; COMB Node = 'LessThan_469~97'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { length_s0_402d[0] LessThan_469~97 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.442 ns) 2.070 ns LessThan_469~102 3 COMB LAB_X29_Y14 " "3: + IC(0.889 ns) + CELL(0.442 ns) = 2.070 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~102'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.331 ns" { LessThan_469~97 LessThan_469~102 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.442 ns) 2.809 ns LessThan_469~104 4 COMB LAB_X29_Y14 " "4: + IC(0.297 ns) + CELL(0.442 ns) = 2.809 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~104'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_469~102 LessThan_469~104 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.442 ns) 3.548 ns LessThan_469~109 5 COMB LAB_X29_Y14 " "5: + IC(0.297 ns) + CELL(0.442 ns) = 3.548 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~109'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_469~104 LessThan_469~109 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.442 ns) 4.287 ns LessThan_469~111 6 COMB LAB_X29_Y14 " "6: + IC(0.297 ns) + CELL(0.442 ns) = 4.287 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~111'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_469~109 LessThan_469~111 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.442 ns) 5.026 ns LessThan_469~116 7 COMB LAB_X29_Y14 " "7: + IC(0.297 ns) + CELL(0.442 ns) = 5.026 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~116'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_469~111 LessThan_469~116 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.442 ns) 5.765 ns LessThan_469~95 8 COMB LAB_X29_Y14 " "8: + IC(0.297 ns) + CELL(0.442 ns) = 5.765 ns; Loc. = LAB_X29_Y14; COMB Node = 'LessThan_469~95'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { LessThan_469~116 LessThan_469~95 } "NODE_NAME" } } } { "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" "" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\vhdl93\\vrfx\\syn_arit.vhd" 1697 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(0.292 ns) 7.173 ns i~3768 9 COMB LAB_X30_Y15 " "9: + IC(1.116 ns) + CELL(0.292 ns) = 7.173 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3768'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.408 ns" { LessThan_469~95 i~3768 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.149 ns) + CELL(0.590 ns) 7.912 ns i~3780 10 COMB LAB_X30_Y15 " "10: + IC(0.149 ns) + CELL(0.590 ns) = 7.912 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3780'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { i~3768 i~3780 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.149 ns) + CELL(0.590 ns) 8.651 ns i~3162 11 COMB LAB_X30_Y15 " "11: + IC(0.149 ns) + CELL(0.590 ns) = 8.651 ns; Loc. = LAB_X30_Y15; COMB Node = 'i~3162'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.739 ns" { i~3780 i~3162 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.149 ns) + CELL(0.738 ns) 9.538 ns temp_s0_402d\[1\] 12 REG LAB_X30_Y15 " "12: + IC(0.149 ns) + CELL(0.738 ns) = 9.538 ns; Loc. = LAB_X30_Y15; REG Node = 'temp_s0_402d\[1\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.887 ns" { i~3162 temp_s0_402d[1] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.154 ns " "Total cell delay = 5.154 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.384 ns " "Total interconnect delay = 4.384 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "9.538 ns" { length_s0_402d[0] LessThan_469~97 LessThan_469~102 LessThan_469~104 LessThan_469~109 LessThan_469~111 LessThan_469~116 LessThan_469~95 i~3768 i~3780 i~3162 temp_s0_402d[1] } "NODE_NAME" } } }  } 0 }
{  "Warning" "WDAT_PRELIMINARY_TIMING" "EP1C6Q240C8 " "Timing characteristics of device EP1C6Q240C8 are preliminary" {  } {  } 0 }
{  "Warning" "WTDB_NO_CLOCKS" "" "Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clkmain1 " "Assuming node clkmain1 is an undefined clock" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 6 -1 0 } }  } 0}  } {  } 0 }
{  "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkmain1 register length_s0_402d\[5\] register length_s0_402d\[5\] 145.84 MHz 6.857 ns Internal " "Clock clkmain1 has Internal fmax of 145.84 MHz between source register length_s0_402d\[5\] and destination register length_s0_402d\[5\] (period= 6.857 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.596 ns + Longest register register " "+ Longest register to register delay is 6.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns length_s0_402d\[5\] 1 REG LC_X31_Y14_N9 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d\[5\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "" { length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.952 ns) + CELL(0.590 ns) 2.542 ns i~17712 2 COMB LC_X30_Y14_N7 " "2: + IC(1.952 ns) + CELL(0.590 ns) = 2.542 ns; Loc. = LC_X30_Y14_N7; COMB Node = 'i~17712'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.542 ns" { length_s0_402d[5] i~17712 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.292 ns) 3.319 ns i~17478 3 COMB LC_X30_Y14_N6 " "3: + IC(0.485 ns) + CELL(0.292 ns) = 3.319 ns; Loc. = LC_X30_Y14_N6; COMB Node = 'i~17478'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.777 ns" { i~17712 i~17478 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.590 ns) 4.649 ns i~7777 4 COMB LC_X29_Y14_N7 " "4: + IC(0.740 ns) + CELL(0.590 ns) = 4.649 ns; Loc. = LC_X29_Y14_N7; COMB Node = 'i~7777'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.330 ns" { i~17478 i~7777 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.164 ns) + CELL(0.292 ns) 6.105 ns i~8104 5 COMB LC_X31_Y14_N8 " "5: + IC(1.164 ns) + CELL(0.292 ns) = 6.105 ns; Loc. = LC_X31_Y14_N8; COMB Node = 'i~8104'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.456 ns" { i~7777 i~8104 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 6.596 ns length_s0_402d\[5\] 6 REG LC_X31_Y14_N9 " "6: + IC(0.182 ns) + CELL(0.309 ns) = 6.596 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d\[5\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "0.491 ns" { i~8104 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.073 ns " "Total cell delay = 2.073 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.523 ns " "Total interconnect delay = 4.523 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "6.596 ns" { length_s0_402d[5] i~17712 i~17478 i~7777 i~8104 length_s0_402d[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "- Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkmain1 destination 2.804 ns + Shortest register " "+ Shortest clock path from clock clkmain1 to destination register is 2.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.328 ns) 1.328 ns clkmain1 1 CLK Pin_29 " "1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "" { clkmain1 } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.711 ns) 2.804 ns length_s0_402d\[5\] 2 REG LC_X31_Y14_N9 " "2: + IC(0.765 ns) + CELL(0.711 ns) = 2.804 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d\[5\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.476 ns" { clkmain1 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.039 ns " "Total cell delay = 2.039 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.765 ns " "Total interconnect delay = 0.765 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkmain1 source 2.804 ns - Longest register " "- Longest clock path from clock clkmain1 to source register is 2.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.328 ns) 1.328 ns clkmain1 1 CLK Pin_29 " "1: + IC(0.000 ns) + CELL(1.328 ns) = 1.328 ns; Loc. = Pin_29; CLK Node = 'clkmain1'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "" { clkmain1 } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.711 ns) 2.804 ns length_s0_402d\[5\] 2 REG LC_X31_Y14_N9 " "2: + IC(0.765 ns) + CELL(0.711 ns) = 2.804 ns; Loc. = LC_X31_Y14_N9; REG Node = 'length_s0_402d\[5\]'" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "1.476 ns" { clkmain1 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.039 ns " "Total cell delay = 2.039 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.765 ns " "Total interconnect delay = 0.765 ns" {  } {  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } }  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "+ Micro clock to output delay of source is 0.224 ns" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "+ Micro setup delay of destination is 0.037 ns" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } }  } 0}  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "6.596 ns" { length_s0_402d[5] i~17712 i~17478 i~7777 i~8104 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" "" "" { Report "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16_Administrator_V1_cmp.qrpt" Compiler "sdram64m16" "Administrator" "V1" "D:\\all_work\\standard\\sdram4m16_L2_42\\db\\sdram64m16.quartus_db" { Floorplan "" "" "2.804 ns" { clkmain1 clkmain1~out0 length_s0_402d[5] } "NODE_NAME" } } }  } 0 }
{  "Info" "IDBC_ERROR_COUNT" "0 5 s s Full compilation sdram64m16 successful was " "Design sdram64m16: Full compilation was successful. 0 errors, 5 warnings" {  } {  } 2 }