📄 sdram64m16.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram64m16 is
port( reset_1: in std_logic;
clkmain1: in std_logic;
xread_1: in std_logic;
xwrite_1: in std_logic;
xlength_3: in std_logic_vector(7 downto 0);
xrasaddr_3: in std_logic_vector(9 downto 0);
xcasaddr_3: in std_logic_vector(7 downto 0);
sdramclk: out std_logic;
ready_p1_402d: out std_logic;
cs_p1_402d: out std_logic;
ras_p1_402d: out std_logic;
cas_p1_402d: out std_logic;
addr_p3_402d: out std_logic_vector(7 downto 0);
a8_p0_402d: out std_logic;
ba_p3_402d: out std_logic;
we_p1_402d: out std_logic;
dqm_p3_402d: out std_logic);
end sdram64m16;
architecture behav of sdram64m16 is
signal refreshask_s1_404u: std_logic;
signal refreshack_s1_402d: std_logic;
signal temp0_s0_401u: std_logic_vector(3 downto 0);
signal temp1_s0_401u: std_logic_vector(3 downto 0);
signal temp2_s0_401u: std_logic_vector(3 downto 0);
signal temp3_s0_401u: std_logic_vector(3 downto 0);
signal temp_s0_402d: std_logic_vector(1 downto 0);
signal length_s0_402d: std_logic_vector(7 downto 0);
signal temp_s0_403d: std_logic_vector(9 downto 0);
-------------------------------------------------------------------------------------
--xlength_3=actual_length-1;
--when write ask,first data must is ready,when ready_p1_402u is low data change
-------------------------------------------------------------------------------------
begin
--------------------------------------------------
b1:block
begin
sdramclk<=clkmain1;
end block b1;
--------------------------------------------------
proc401:process(clkmain1,reset_1)
begin
if(reset_1='0')then
temp0_s0_401u<="0001";
temp1_s0_401u<="0100";
temp2_s0_401u<="0100";
temp3_s0_401u<="0101";
elsif(clkmain1'event and clkmain1='1')then
if(temp_s0_402d="11")then
if(temp1_s0_401u="0000")then
if(refreshask_s1_404u='0')then
temp0_s0_401u<="0100";
temp1_s0_401u<="0000";
temp2_s0_401u<="0000";
temp3_s0_401u<="0000";
elsif(xread_1='0')then
temp0_s0_401u<="0110";
temp1_s0_401u<="1000";
temp2_s0_401u<="0011";
temp3_s0_401u<="0000";
elsif(xwrite_1='0')then
temp0_s0_401u<="0110";
temp1_s0_401u<="0111";
temp2_s0_401u<="0010";
temp3_s0_401u<="0000";
else
temp0_s0_401u<=temp1_s0_401u;
temp1_s0_401u<=temp2_s0_401u;
temp2_s0_401u<=temp3_s0_401u;
temp3_s0_401u<="0000";
end if;
else
temp0_s0_401u<=temp1_s0_401u;
temp1_s0_401u<=temp2_s0_401u;
temp2_s0_401u<=temp3_s0_401u;
temp3_s0_401u<="0000";
end if;
end if;
end if;
end process proc401;
proc402:process(clkmain1,reset_1)
begin
if(reset_1='0')then
cs_p1_402d<='1';
ras_p1_402d<='1';
cas_p1_402d<='1';
a8_p0_402d<='0';
we_p1_402d<='1';
dqm_p3_402d<='1';
ready_p1_402d<='1';
refreshack_s1_402d<='1';
temp_s0_402d<="00";
elsif(clkmain1'event and clkmain1='1')then
if(temp0_s0_401u="0000")then ----------------------------------idle--------------
if(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
else
cs_p1_402d<='1';
ras_p1_402d<='1';
cas_p1_402d<='1';
a8_p0_402d<='0';
we_p1_402d<='1';
ready_p1_402d<='1';
refreshack_s1_402d<='1';
temp_s0_402d<="11";
end if;
elsif(temp0_s0_401u="0001")then -------------------------------total charge-----------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
a8_p0_402d<='1';
we_p1_402d<='0';
dqm_p3_402d<='1';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
a8_p0_402d<='0';
we_p1_402d<='1';
temp_s0_402d<="11";
elsif(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0010")then -------------------------------write charge-----------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
we_p1_402d<='0';
dqm_p3_402d<='1';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
we_p1_402d<='1';
dqm_p3_402d<='0';
temp_s0_402d<="11";
elsif(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0011")then -------------------------------read charge-----------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
we_p1_402d<='0';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
we_p1_402d<='1';
temp_s0_402d<="11";
elsif(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0100")then ----------------------------------auto refresh--------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
cas_p1_402d<='0';
refreshack_s1_402d<='0';
length_s0_402d<="00000000";
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
cas_p1_402d<='1';
refreshack_s1_402d<='1';
temp_s0_402d<="10";
elsif(temp_s0_402d="10")then ----idle 7
if(length_s0_402d>="00000101")then
temp_s0_402d<="11";
else
length_s0_402d<=length_s0_402d+'1';
end if;
elsif(temp_s0_402d>="11")then
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0101")then -------------------------------------------set--------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
cas_p1_402d<='0';
we_p1_402d<='0';
addr_p3_402d<="00100111"; --//mode set,full page CL=2//---
ba_p3_402d<='0';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
cas_p1_402d<='1';
we_p1_402d<='1';
temp_s0_402d<="11";
elsif(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0110")then ----------------------------------row active--------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
ras_p1_402d<='0';
dqm_p3_402d<='0'; ----------from initial and write operation HIGH to LOW
addr_p3_402d<=xrasaddr_3(7 downto 0);
a8_p0_402d<=xrasaddr_3(8);
ba_p3_402d<=xrasaddr_3(9);
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
ras_p1_402d<='1';
a8_p0_402d<='0';
length_s0_402d<="00000000";
temp_s0_402d<="11";
elsif(temp_s0_402d>="11")then ----idle 2
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u="0111")then ----------------------------------write--------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
cas_p1_402d<='0';
we_p1_402d<='0';
addr_p3_402d<=xcasaddr_3;
ba_p3_402d<=xrasaddr_3(9);
ready_p1_402d<='0';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then ----idle N-1
cs_p1_402d<='1';
cas_p1_402d<='1';
we_p1_402d<='1';
if(length_s0_402d>=xlength_3)then
dqm_p3_402d<='1'; ----------dqm is need,this clk write must be forbid
ready_p1_402d<='1'; ----------and till next clk precharge interrupt write operation
temp_s0_402d<="11";
else
length_s0_402d<=length_s0_402d+'1';
end if;
elsif(temp_s0_402d>="11")then
temp_s0_402d<="00";
end if;
elsif(temp0_s0_401u>="1000")then ----------------------------------read-----------
if(temp_s0_402d="00")then
cs_p1_402d<='0';
cas_p1_402d<='0';
addr_p3_402d<=xcasaddr_3;
ba_p3_402d<=xrasaddr_3(9);
ready_p1_402d<='0';
temp_s0_402d<="01";
elsif(temp_s0_402d="01")then
cs_p1_402d<='1';
cas_p1_402d<='1';
if(length_s0_402d>=xlength_3)then
ready_p1_402d<='1';
temp_s0_402d<="11";
else
length_s0_402d<=length_s0_402d+'1';
end if;
elsif(temp_s0_402d>="11")then
temp_s0_402d<="00";
end if;
end if;
end if;
end process proc402;
proc403:process(clkmain1,reset_1)
begin
if(reset_1='0')then
temp_s0_403d<="0000000000";
elsif(clkmain1'event and clkmain1='1')then
if(temp_s0_403d>="1111110000")then
temp_s0_403d<="0000000000";
else
temp_s0_403d<=temp_s0_403d+'1';
end if;
end if;
end process proc403;
proc404:process(clkmain1,reset_1)
begin
if(reset_1='0')then
refreshask_s1_404u<='1';
elsif(clkmain1'event and clkmain1='1')then
if(refreshack_s1_402d='0')then
refreshask_s1_404u<='1';
elsif(temp_s0_403d="1111110000")then
refreshask_s1_404u<='0';
end if;
end if;
end process proc404;
end behav;⌨️ 快捷键说明
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