i2c.rpt

I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能

Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   37/11
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
(unused)                            0    FB6_1           (b)      
data_bus<2>                         7    FB6_2      55   I/O   I/O
data_bus<4>                         7    FB6_3      56   I/O   I/O
(unused)                            0    FB6_4           (b)      
data_bus<6>                         7    FB6_5      60   I/O   I/O
uc_ctrl_rsta                        5    FB6_6           (b)   (b)
uc_ctrl_mien                        3    FB6_7           (b)   (b)
uc_ctrl_men                         3    FB6_8           (b)   (b)
uc_ctrl_madr<7>                     3    FB6_9           (b)   (b)
uc_ctrl_madr<6>                     3    FB6_10          (b)   (b)
uc_ctrl_madr<4>                     3    FB6_11          (b)   (b)
data_bus<7>                         7    FB6_12     61   I/O   I/O
(unused)                            0    FB6_13     62   I/O     I
(unused)                            0    FB6_14     63   I/O     I
uc_ctrl_madr<2>                     3    FB6_15          (b)   (b)
(unused)                            0    FB6_16     65   I/O      

Signals Used by Logic in Function Block
  1: N_PZ_560          14: "i2c_ctrl_mbdr_i2c<4>" 
                                             27: uc_ctrl_ds_int.COMB 
  2: N_PZ_564          15: "i2c_ctrl_mbdr_i2c<6>" 
                                             28: "uc_ctrl_madr<2>" 
  3: "data_bus<2>"     16: "i2c_ctrl_mbdr_i2c<7>" 
                                             29: "uc_ctrl_madr<4>" 
  4: "data_bus<2>".PIN 17: i2c_ctrl_scl_state_fft1 
                                             30: "uc_ctrl_madr<6>" 
  5: "data_bus<4>"     18: i2c_ctrl_scl_state_fft2 
                                             31: "uc_ctrl_madr<7>" 
  6: "data_bus<4>".PIN 19: i2c_ctrl_scl_state_fft3 
                                             32: uc_ctrl_men 
  7: "data_bus<6>"     20: i2c_ctrl_srw      33: uc_ctrl_mien 
  8: "data_bus<6>".PIN 21: mcf               34: uc_ctrl_mtx 
  9: "data_bus<7>"     22: r_w               35: uc_ctrl_prs_state_fft1 
 10: "data_bus<7>".PIN 23: reset             36: uc_ctrl_prs_state_fft2 
 11: i2c_ctrl_maas     24: uc_ctrl_addr_en   37: uc_ctrl_rsta 
 12: i2c_ctrl_mal      25: uc_ctrl_cntrl_en  38: uc_ctrl_stat_en 
 13: "i2c_ctrl_mbdr_i2c<2>" 
                       26: uc_ctrl_data_en  

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
data_bus<2>       ..X.........X......X.XXXXXXX......XXXX.. 14      14
data_bus<4>       ....X......X.X.......XXXXXX.X....XXX.X.. 14      14
data_bus<6>       ......X...X...X......XXXXXX..X..X.XX.X.. 14      14
uc_ctrl_rsta      .X.X............XXX...X.............X... 7       7
uc_ctrl_mien      .X.....X..............X.........X....... 4       4
uc_ctrl_men       .X.......X............X........X........ 4       4
uc_ctrl_madr<7>   X........X............X.......X......... 4       4
uc_ctrl_madr<6>   X......X..............X......X.......... 4       4
uc_ctrl_madr<4>   X....X................X.....X........... 4       4
data_bus<7>       ........X......X....XXXXXXX...XX..XX.X.. 14      14
uc_ctrl_madr<2>   X..X..................X....X............ 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB7 ***********************************
Number of signals used by logic mapping into function block:  24
Number of function block inputs used/remaining:               24/16
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   35/13
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
i2c_ctrl_shift_reg<6>               5    FB7_1      81   I/O     I
i2c_ctrl_mbdr_i2c<4>                3    FB7_2           (b)   (b)
i2c_ctrl_shift_reg<5>               5    FB7_3      80   I/O     I
i2c_ctrl_shift_reg<4>               5    FB7_4      79   I/O     I
i2c_ctrl_shift_reg<3>               5    FB7_5      78   I/O     I
i2c_ctrl_mbdr_i2c<3>                3    FB7_6           (b)   (b)
i2c_ctrl_mbdr_i2c<2>                3    FB7_7           (b)   (b)
i2c_ctrl_mbdr_i2c<1>                3    FB7_8           (b)   (b)
i2c_ctrl_clk_cnt<1>                 3    FB7_9           (b)   (b)
i2c_ctrl_mif                        3    FB7_10          (b)   (b)
i2c_ctrl_mal                        3    FB7_11          (b)   (b)
i2c_ctrl_shift_reg<2>               5    FB7_12     77   I/O     I
i2c_ctrl_sda_out_reg_d1             2    FB7_13          (b)   (b)
i2c_ctrl_mbdr_i2c<6>                3    FB7_14     75   I/O     I
i2c_ctrl_mbdr_i2c<5>                3    FB7_15     74   I/O     I
i2c_ctrl_scl_in                     2    FB7_16          (b)   (b)

Signals Used by Logic in Function Block
  1: N_PZ_662           9: "i2c_ctrl_shift_reg<3>" 
                                             17: scl.PIN 
  2: N_PZ_667          10: "i2c_ctrl_shift_reg<4>" 
                                             18: uc_ctrl_mal_bit_reset 
  3: i2c_ctrl__n0170   11: "i2c_ctrl_shift_reg<5>" 
                                             19: "uc_ctrl_mbdr_micro<2>" 
  4: i2c_ctrl__n0171   12: "i2c_ctrl_shift_reg<6>" 
                                             20: "uc_ctrl_mbdr_micro<3>" 
  5: "i2c_ctrl_clk_cnt<1>" 
                       13: i2c_ctrl_shift_reg_en 
                                             21: "uc_ctrl_mbdr_micro<4>" 
  6: i2c_ctrl_sda_out_reg 
                       14: i2c_ctrl_shift_reg_ld 
                                             22: "uc_ctrl_mbdr_micro<5>" 
  7: "i2c_ctrl_shift_reg<1>" 
                       15: i2c_ctrl_state_ffd1 
                                             23: "uc_ctrl_mbdr_micro<6>" 
  8: "i2c_ctrl_shift_reg<2>" 
                       16: i2c_ctrl_state_ffd3 
                                             24: uc_ctrl_mif_bit_reset 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
i2c_ctrl_shift_reg<6> 
                  ..........XXXX........X................. 5       5
i2c_ctrl_mbdr_i2c<4> 
                  .........X....XX........................ 3       3
i2c_ctrl_shift_reg<5> 
                  .........XX.XX.......X.................. 5       5
i2c_ctrl_shift_reg<4> 
                  ........XX..XX......X................... 5       5
i2c_ctrl_shift_reg<3> 
                  .......XX...XX.....X.................... 5       5
i2c_ctrl_mbdr_i2c<3> 
                  ........X.....XX........................ 3       3
i2c_ctrl_mbdr_i2c<2> 
                  .......X......XX........................ 3       3
i2c_ctrl_mbdr_i2c<1> 
                  ......X.......XX........................ 3       3
i2c_ctrl_clk_cnt<1> 
                  XX..X................................... 3       3
i2c_ctrl_mif      ...X...................X................ 2       2
i2c_ctrl_mal      ..X..............X...................... 2       2
i2c_ctrl_shift_reg<2> 
                  ......XX....XX....X..................... 5       5
i2c_ctrl_sda_out_reg_d1 
                  .....X.................................. 1       1
i2c_ctrl_mbdr_i2c<6> 
                  ...........X..XX........................ 3       3
i2c_ctrl_mbdr_i2c<5> 
                  ..........X...XX........................ 3       3
i2c_ctrl_scl_in   ................X....................... 1       1
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
*********************************** FB8 ***********************************
Number of signals used by logic mapping into function block:  32
Number of function block inputs used/remaining:               32/8
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   27/21
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
uc_ctrl_mbdr_micro<7>               3    FB8_1      66   I/O   (b)
uc_ctrl_mbdr_micro<6>               3    FB8_2      67   I/O   (b)
uc_ctrl_mbdr_micro<5>               3    FB8_3      68   I/O   (b)
uc_ctrl_mbdr_micro<4>               3    FB8_4      69   I/O   (b)
uc_ctrl_mbdr_micro<1>               3    FB8_5           (b)   (b)
uc_ctrl_madr<3>                     3    FB8_6           (b)   (b)
uc_ctrl_madr<1>                     3    FB8_7           (b)   (b)
uc_ctrl_madr<0>                     2    FB8_8           (b)   (b)
uc_ctrl_as_int_d1                   2    FB8_9           (b)   (b)
uc_ctrl_stat_en                     2    FB8_10          (b)   (b)
uc_ctrl_data_en                     2    FB8_11          (b)   (b)
uc_ctrl_mbdr_micro<2>               3    FB8_12     70   I/O   (b)
uc_ctrl_cntrl_en                    2    FB8_13          (b)   (b)
uc_ctrl_mbdr_micro<0>               3    FB8_14     71   I/O   (b)
uc_ctrl_addr_en                     2    FB8_15          (b)   (b)
uc_ctrl_mbdr_micro<3>               3    FB8_16     72   I/O   (b)

Signals Used by Logic in Function Block
  1: N_PZ_559          12: "data_bus<1>".PIN 23: "uc_ctrl_madr<1>" 
  2: N_PZ_560          13: "data_bus<2>".PIN 24: "uc_ctrl_madr<3>" 
  3: "addr_bus<0>"     14: "data_bus<3>".PIN 25: "uc_ctrl_mbdr_micro<0>" 
  4: "addr_bus<1>"     15: "data_bus<4>".PIN 26: "uc_ctrl_mbdr_micro<1>" 
  5: "addr_bus<2>"     16: "data_bus<5>".PIN 27: "uc_ctrl_mbdr_micro<2>" 
  6: "addr_bus<3>"     17: "data_bus<6>".PIN 28: "uc_ctrl_mbdr_micro<3>" 
  7: "addr_bus<4>"     18: "data_bus<7>".PIN 29: "uc_ctrl_mbdr_micro<4>" 
  8: "addr_bus<5>"     19: reset             30: "uc_ctrl_mbdr_micro<5>" 
  9: "addr_bus<6>"     20: uc_ctrl_address_match 
                                             31: "uc_ctrl_mbdr_micro<6>" 
 10: "addr_bus<7>"     21: uc_ctrl_as_int    32: "uc_ctrl_mbdr_micro<7>" 
 11: "data_bus<0>".PIN 22: "uc_ctrl_madr<0>"

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
uc_ctrl_mbdr_micro<7> 
                  X................XX............X........ 4       4
uc_ctrl_mbdr_micro<6> 
                  X...............X.X...........X......... 4       4
uc_ctrl_mbdr_micro<5> 
                  X..............X..X..........X.......... 4       4
uc_ctrl_mbdr_micro<4> 
                  X.............X...X.........X........... 4       4
uc_ctrl_mbdr_micro<1> 
                  X..........X......X......X.............. 4       4
uc_ctrl_madr<3>   .X...........X....X....X................ 4       4
uc_ctrl_madr<1>   .X.........X......X...X................. 4       4
uc_ctrl_madr<0>   .X................X..X.................. 3       3
uc_ctrl_as_int_d1 
                  ..................X.X................... 2       2
uc_ctrl_stat_en   ..XXXXXXXX........XX.................... 10      10
uc_ctrl_data_en   ..XXXXXXXX........XX.................... 10      10
uc_ctrl_mbdr_micro<2> 
                  X...........X.....X.......X............. 4       4
uc_ctrl_cntrl_en  ..XXXXXXXX........XX.................... 10      10
uc_ctrl_mbdr_micro<0> 
                  X.........X.......X.....X............... 4       4
uc_ctrl_addr_en   ..XXXXXXXX........XX.................... 10      10
uc_ctrl_mbdr_micro<3> 
                  X............X....X........X............ 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell