📄 i2c.rpt
字号:
24: sda
6: "i2c_ctrl_bit_cnt<1>"
16: i2c_ctrl_scl_state_fft3
25: sda.PIN
7: "i2c_ctrl_bit_cnt<2>"
17: i2c_ctrl_sm_stop 26: uc_ctrl_men
8: "i2c_ctrl_clk_cnt<0>"
18: i2c_ctrl_state_ffd1
27: uc_ctrl_mtx
9: "i2c_ctrl_clk_cnt<1>"
19: i2c_ctrl_state_ffd2
28: uc_ctrl_rsta
10: "i2c_ctrl_clk_cnt<2>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
mcf ..X.XXX................................. 4 4
i2c_ctrl__n0073 .................XXX.....X.............. 4 4
i2c_ctrl_i2c_header_en
.................XXX..X................. 4 4
i2c_ctrl_shift_reg_ld
...........XX....XXX..X...X............. 7 7
i2c_ctrl_sm_stop ...X......X.X...XXXX...XXX.............. 10 10
i2c_ctrl_state_ffd1
...X......X.X....XXX.XXXXX.............. 11 11
i2c_ctrl_state_ffd2
..XXXXX...XXX....XXX.XXXXXX............. 17 17
i2c_ctrl_state_ffd3
..X.XXX...X......XXX..X..X.............. 10 10
i2c_ctrl_bit_cnt<1>
X...XX...........XXX..X................. 7 7
i2c_ctrl_scl_state_fft2
.XXXXXXXXX...XXX....X......X............ 14 14
i2c_ctrl_bit_cnt<2>
X...XXX..........XXX..X................. 8 8
i2c_ctrl_scl_state_fft3
.XXXXXXXXX...XXX...........X............ 13 13
i2c_ctrl_bit_cnt<0>
....X............XXX..X................. 5 5
i2c_ctrl__n0159 X.X.XXX..........XXX..X................. 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block: 29
Number of function block inputs used/remaining: 29/11
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
(unused) 0 FB4_1 114 I/O I
N_PZ_667 3 FB4_2 116 I/O I
i2c_ctrl_scl_out_reg 3 FB4_3 117 I/O I
i2c_ctrl_clk_cnt<0> 5 FB4_4 (b) (b)
i2c_ctrl_msta_rst 5 FB4_5 118 I/O I
i2c_ctrl_scl_state_fft1 5 FB4_6 (b) (b)
i2c_ctrl_sda_out_reg 13 FB4_7 (b) (b)
i2c_ctrl__n0170 5 FB4_8 (b) (b)
i2c_ctrl_bus_busy 3 FB4_9 (b) (b)
i2c_ctrl_gen_stop 3 FB4_10 (b) (b)
i2c_ctrl_gen_start 3 FB4_11 (b) (b)
i2c_ctrl_arb_lost 4 FB4_12 119 I/O I
i2c_ctrl__n0153 3 FB4_13 120 I/O I
i2c_ctrl_stop_scl_reg 5 FB4_14 121 I/O (b)
i2c_ctrl_msta_d1 2 FB4_15 (b) (b)
i2c_ctrl_clk_cnt<2> 6 FB4_16 122 I/O (b)
Signals Used by Logic in Function Block
1: N_PZ_641 11: "i2c_ctrl_clk_cnt<2>"
21: i2c_ctrl_scl_state_fft2
2: N_PZ_662 12: i2c_ctrl_detect_stop
22: i2c_ctrl_scl_state_fft3
3: N_PZ_667 13: i2c_ctrl_gen_start
23: i2c_ctrl_sda_out_reg
4: N_PZ_683 14: i2c_ctrl_gen_stop 24: i2c_ctrl_sm_stop
5: i2c_ctrl__n0153 15: i2c_ctrl_master_sda
25: i2c_ctrl_stop_scl_reg
6: i2c_ctrl_arb_lost 16: i2c_ctrl_master_slave
26: scl
7: i2c_ctrl_bus_busy 17: i2c_ctrl_msta_d1 27: uc_ctrl_mal_bit_reset
8: i2c_ctrl_bus_busy_d1
18: i2c_ctrl_msta_rst 28: uc_ctrl_msta
9: "i2c_ctrl_clk_cnt<0>"
19: i2c_ctrl_scl_in 29: uc_ctrl_rsta
10: "i2c_ctrl_clk_cnt<1>"
20: i2c_ctrl_scl_state_fft1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
N_PZ_667 ...................XXX.................. 3 3
i2c_ctrl_scl_out_reg
...................XXX.................. 3 3
i2c_ctrl_clk_cnt<0>
..X.X...XXX........XXX..X...X........... 10 10
i2c_ctrl_msta_rst
...X.X.........X.X.XXX.................. 7 7
i2c_ctrl_scl_state_fft1
....X.X.XXX.X..X..XXXX.................. 11 11
i2c_ctrl_sda_out_reg
X...XX..XXX..XX....XXXXX....X........... 14 14
i2c_ctrl__n0170 .....X.X...XXX.X.......X..X.X........... 9 9
i2c_ctrl_bus_busy
...........X.............X.............. 2 2
i2c_ctrl_gen_stop
.....X.....X.X..X..........X............ 5 5
i2c_ctrl_gen_start
............X...X........X.X............ 4 4
i2c_ctrl_arb_lost
...X.X.........X...XXX.................. 6 6
i2c_ctrl__n0153 .XX.X....XX............................. 5 5
i2c_ctrl_stop_scl_reg
X....X.......X.....XXX.XX............... 8 8
i2c_ctrl_msta_d1 ...........................X............ 1 1
i2c_ctrl_clk_cnt<2>
.XX.X...XXX........XX...X...X........... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB5 ***********************************
Number of signals used by logic mapping into function block: 28
Number of function block inputs used/remaining: 28/12
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 39/9
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
n7280 14 FB5_1 89TCK/I/O (b)
i2c_ctrl_srw 3 FB5_2 (b) (b)
i2c_ctrl_mbdr_i2c<0> 3 FB5_3 88 I/O (b)
i2c_ctrl_mbdr_i2c<7> 3 FB5_4 87 I/O (b)
i2c_ctrl_maas 4 FB5_5 86 I/O (b)
i2c_ctrl_i2c_header<1> 4 FB5_6 (b) (b)
i2c_ctrl_i2c_header<0> 4 FB5_7 (b) (b)
i2c_ctrl_i2c_header<7> 4 FB5_8 (b) (b)
i2c_ctrl_i2c_header<6> 4 FB5_9 (b) (b)
i2c_ctrl_i2c_header<5> 4 FB5_10 (b) (b)
i2c_ctrl_i2c_header<4> 4 FB5_11 (b) (b)
i2c_ctrl_slave_sda 4 FB5_12 84 I/O (b)
i2c_ctrl_i2c_header<3> 4 FB5_13 (b) (b)
i2c_ctrl_master_sda 4 FB5_14 83 I/O (b)
i2c_ctrl_shift_reg_en 3 FB5_15 82 I/O (b)
i2c_ctrl_i2c_header<2> 4 FB5_16 (b) (b)
Signals Used by Logic in Function Block
1: "i2c_ctrl_i2c_header<0>"
11: i2c_ctrl_master_slave
20: "uc_ctrl_madr<2>"
2: "i2c_ctrl_i2c_header<1>"
12: i2c_ctrl_shift_out
21: "uc_ctrl_madr<3>"
3: "i2c_ctrl_i2c_header<2>"
13: "i2c_ctrl_shift_reg<0>"
22: "uc_ctrl_madr<4>"
4: "i2c_ctrl_i2c_header<3>"
14: i2c_ctrl_state_ffd1
23: "uc_ctrl_madr<5>"
5: "i2c_ctrl_i2c_header<4>"
15: i2c_ctrl_state_ffd2
24: "uc_ctrl_madr<6>"
6: "i2c_ctrl_i2c_header<5>"
16: i2c_ctrl_state_ffd3
25: "uc_ctrl_madr<7>"
7: "i2c_ctrl_i2c_header<6>"
17: n7280 26: uc_ctrl_mbcr_wr
8: "i2c_ctrl_i2c_header<7>"
18: sda 27: uc_ctrl_men
9: i2c_ctrl_i2c_header_en
19: "uc_ctrl_madr<1>" 28: uc_ctrl_txak
10: i2c_ctrl_maas
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
n7280 .XXXXXXX..........XXXXXXX............... 14 14
i2c_ctrl_srw X............XXX..........X............. 5 5
i2c_ctrl_mbdr_i2c<0>
............XX.X..........X............. 4 4
i2c_ctrl_mbdr_i2c<7>
...........X.X.X..........X............. 4 4
i2c_ctrl_maas .........X...XXXX........XX............. 7 7
i2c_ctrl_i2c_header<1>
X.......X.................X............. 3 3
i2c_ctrl_i2c_header<0>
........X........X........X............. 3 3
i2c_ctrl_i2c_header<7>
......X.X.................X............. 3 3
i2c_ctrl_i2c_header<6>
.....X..X.................X............. 3 3
i2c_ctrl_i2c_header<5>
....X...X.................X............. 3 3
i2c_ctrl_i2c_header<4>
...X....X.................X............. 3 3
i2c_ctrl_slave_sda
.........X.X.XXX..........XX............ 7 7
i2c_ctrl_i2c_header<3>
..X.....X.................X............. 3 3
i2c_ctrl_master_sda
...........X.XXX..........XX............ 6 6
i2c_ctrl_shift_reg_en
..........X..XXX..........X............. 5 5
i2c_ctrl_i2c_header<2>
.X......X.................X............. 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB6 ***********************************
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
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