📄 i2c.rpt
字号:
Name # Type Use Style
addr_bus<0> FB7_1 81 I/O I
addr_bus<10> FB2_12 110 I/O I
addr_bus<11> FB2_13 111 I/O I
addr_bus<12> FB2_15 112 I/O I
addr_bus<13> FB2_16 113 I/O I
addr_bus<14> FB3_2 97 I/O I
addr_bus<15> FB3_3 96 I/O I
addr_bus<16> FB3_4 94 I/O I
addr_bus<17> FB3_5 93 I/O I
addr_bus<18> FB3_12 92 I/O I
addr_bus<19> FB3_14 91 I/O I
addr_bus<1> FB7_3 80 I/O I
addr_bus<20> FB3_15 90 I/O I
addr_bus<21> FB4_1 114 I/O I
addr_bus<22> FB4_2 116 I/O I
addr_bus<23> FB4_3 117 I/O I
addr_bus<2> FB7_4 79 I/O I
addr_bus<3> FB7_5 78 I/O I
addr_bus<4> FB7_12 77 I/O I
addr_bus<5> FB7_14 75 I/O I
addr_bus<6> FB7_15 74 I/O I
addr_bus<7> FB4_5 118 I/O I
addr_bus<8> FB4_12 119 I/O I
addr_bus<9> FB4_13 120 I/O I
as FB1_5 102 I/O I
clk 128 GCK/I GCK
ds FB1_12 101 I/O I
r_w FB6_13 62 I/O I
reset FB6_14 63 I/O I
End of Resources Used by Successfully Mapped Logic
Legend: PU - Pull Up
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 32 32 39 0/4 6
FB2 7 38 38 19 1/2 7
FB3 14 28 28 48 1/0 8
FB4 15 29 29 48 0/0 8
FB5 16 28 28 39 0/0 6
FB6 11 38 38 37 0/4 7
FB7 16 24 24 35 0/0 7
FB8 16 32 32 27 0/0 7
FB9 12 34 34 32 1/0 7
FB10 1 6 6 2 0/0 7
FB11 0 0 0 0 0/0 7
FB12 0 0 0 0 0/0 6
FB13 0 0 0 0 0/0 7
FB14 0 0 0 0 0/0 7
FB15 0 0 0 0 0/0 8
FB16 0 0 0 0 0/0 7
---- ----- ----- -----
124 326 3/10 112
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block: 32
Number of function block inputs used/remaining: 32/8
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 7/1
Number of PLA product terms used/remaining: 39/9
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
scl 3 FB1_1 106 I/O I/O
uc_ctrl_madr<5> 3 FB1_2 (b) (b)
uc_ctrl_mal_bit_reset 4 FB1_3 104TDO/I/O (b)
sda 2 FB1_4 103 I/O I/O
uc_ctrl_as_int 1 FB1_5 102 I/O I
uc_ctrl_msta 3 FB1_6 (b) (b)
uc_ctrl_mtx 3 FB1_7 (b) (b)
uc_ctrl_mbcr_wr 4 FB1_8 (b) (b)
i2c_ctrl_master_slave 3 FB1_9 (b) (b)
N_PZ_564 1 FB1_10 (b) (b)
N_PZ_560 1 FB1_11 (b) (b)
uc_ctrl_ds_int 5 FB1_12 101 I/O I
data_bus<5> 7 FB1_13 100 I/O I/O
data_bus<0> 6 FB1_14 99 I/O I/O
N_PZ_559 1 FB1_15 (b) (b)
uc_ctrl_mif_bit_reset 4 FB1_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_560 12: "i2c_ctrl_mbdr_i2c<5>"
23: "uc_ctrl_madr<0>"
2: N_PZ_564 13: i2c_ctrl_msta_rst 24: "uc_ctrl_madr<5>"
3: "data_bus<0>" 14: i2c_ctrl_rxak 25: uc_ctrl_mal_bit_reset
4: "data_bus<2>".PIN 15: i2c_ctrl_scl_out_reg
26: uc_ctrl_mbcr_wr
5: "data_bus<4>".PIN 16: r_w 27: uc_ctrl_mif_bit_reset
6: "data_bus<5>" 17: reset 28: uc_ctrl_msta
7: "data_bus<5>".PIN 18: sda.PIN 29: uc_ctrl_mtx
8: i2c_ctrl__n0073 19: uc_ctrl_addr_en 30: uc_ctrl_prs_state_fft1
9: i2c_ctrl__n0096 20: uc_ctrl_cntrl_en 31: uc_ctrl_prs_state_fft2
10: i2c_ctrl_bus_busy 21: uc_ctrl_data_en 32: uc_ctrl_stat_en
11: "i2c_ctrl_mbdr_i2c<0>"
22: uc_ctrl_ds_int.COMB
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
scl .......X......X..X...................... 3 3
uc_ctrl_madr<5> X.....X.........X......X................ 4 4
uc_ctrl_mal_bit_reset
....X..........XX.......X....XXX........ 7 7
sda ........X............................... 1 1
uc_ctrl_msta .X....X.....X...X..........X............ 5 5
uc_ctrl_mtx .X..X...........X...........X........... 4 4
uc_ctrl_mbcr_wr .X..............X........X...XX......... 5 5
i2c_ctrl_master_slave
.........X.................X............ 2 2
N_PZ_564 ...............X...X.........XX......... 4 4
N_PZ_560 ...............X..X..........XX......... 4 4
uc_ctrl_ds_int ...............XX.XXX........XXX........ 8 8
data_bus<5> .....X...X.X...XX.XXXX.X...X.XXX........ 14 14
data_bus<0> ..X.......X..X.XX.XXXXX......XXX........ 13 13
N_PZ_559 ...............X....X........XX......... 4 4
uc_ctrl_mif_bit_reset
...X...........XX.........X..XXX........ 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 3/5
Number of PLA product terms used/remaining: 19/29
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
dtack 3 FB2_1 107 I/O O
data_bus<1> 6 FB2_2 108 I/O I/O
(unused) 0 FB2_3 (b)
(unused) 0 FB2_4 (b)
data_bus<3> 6 FB2_5 109 I/O I/O
(unused) 0 FB2_6 (b)
(unused) 0 FB2_7 (b)
(unused) 0 FB2_8 (b)
i2c_ctrl_bus_busy_d1 2 FB2_9 (b) (b)
uc_ctrl_address_match 2 FB2_10 (b) (b)
uc_ctrl_prs_state_fft1 4 FB2_11 (b) (b)
(unused) 0 FB2_12 110 I/O I
(unused) 0 FB2_13 111 I/O I
uc_ctrl_prs_state_fft2 3 FB2_14 (b) (b)
(unused) 0 FB2_15 112 I/O I
(unused) 0 FB2_16 113 I/O I
Signals Used by Logic in Function Block
1: "addr_bus<10>" 14: "addr_bus<23>" 27: uc_ctrl_address_match
2: "addr_bus<11>" 15: "addr_bus<8>" 28: uc_ctrl_as_int_d1
3: "addr_bus<12>" 16: "addr_bus<9>" 29: uc_ctrl_cntrl_en
4: "addr_bus<13>" 17: as 30: uc_ctrl_data_en
5: "addr_bus<14>" 18: "data_bus<1>" 31: uc_ctrl_ds_int
6: "addr_bus<15>" 19: "data_bus<3>" 32: uc_ctrl_ds_int.COMB
7: "addr_bus<16>" 20: i2c_ctrl_bus_busy 33: "uc_ctrl_madr<1>"
8: "addr_bus<17>" 21: "i2c_ctrl_mbdr_i2c<1>"
34: "uc_ctrl_madr<3>"
9: "addr_bus<18>" 22: "i2c_ctrl_mbdr_i2c<3>"
35: uc_ctrl_prs_state_fft1
10: "addr_bus<19>" 23: i2c_ctrl_mif 36: uc_ctrl_prs_state_fft2
11: "addr_bus<20>" 24: r_w 37: uc_ctrl_stat_en
12: "addr_bus<21>" 25: reset 38: uc_ctrl_txak
13: "addr_bus<22>" 26: uc_ctrl_addr_en
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
dtack ........................X.........XX.... 3 3
data_bus<1> .................X..X.XXXX..XX.XX.XXX... 13 13
data_bus<3> ..................X..X.XXX..XX.X.XXXXX.. 13 13
i2c_ctrl_bus_busy_d1
...................X.................... 1 1
uc_ctrl_address_match
XXXXXXXXXXXXXXXXX.......X..X............ 19 19
uc_ctrl_prs_state_fft1
................X.......X.XX......XX.... 6 6
uc_ctrl_prs_state_fft2
........................X.XX..X...XX.... 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block: 28
Number of function block inputs used/remaining: 28/12
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Signal Total Loc Pin Pin Pin
Name Pt # Type Use
mcf 3 FB3_1 98 I/O O
(unused) 0 FB3_2 97 I/O I
(unused) 0 FB3_3 96 I/O I
i2c_ctrl__n0073 2 FB3_4 94 I/O I
i2c_ctrl_i2c_header_en 3 FB3_5 93 I/O I
i2c_ctrl_shift_reg_ld 6 FB3_6 (b) (b)
i2c_ctrl_sm_stop 5 FB3_7 (b) (b)
i2c_ctrl_state_ffd1 7 FB3_8 (b) (b)
i2c_ctrl_state_ffd2 7 FB3_9 (b) (b)
i2c_ctrl_state_ffd3 6 FB3_10 (b) (b)
i2c_ctrl_bit_cnt<1> 5 FB3_11 (b) (b)
i2c_ctrl_scl_state_fft2 5 FB3_12 92 I/O I
i2c_ctrl_bit_cnt<2> 5 FB3_13 (b) (b)
i2c_ctrl_scl_state_fft3 9 FB3_14 91 I/O I
i2c_ctrl_bit_cnt<0> 5 FB3_15 90 I/O I
i2c_ctrl__n0159 5 FB3_16 (b) (b)
Signals Used by Logic in Function Block
1: N_PZ_668 11: i2c_ctrl_detect_stop
20: i2c_ctrl_state_ffd3
2: i2c_ctrl__n0153 12: "i2c_ctrl_i2c_header<0>"
21: i2c_ctrl_stop_scl_reg
3: i2c_ctrl__n0159 13: i2c_ctrl_master_slave
22: n7280
4: i2c_ctrl_arb_lost 14: i2c_ctrl_scl_state_fft1
23: scl
5: "i2c_ctrl_bit_cnt<0>"
15: i2c_ctrl_scl_state_fft2
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