📄 i2c.rpt
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cpldfit: version F.26 Xilinx Inc.
Fitter Report
Design Name: i2c Date: 12-20-2002, 4:29PM
Device Used: XCR3256XL-7-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
124/256 ( 48%) 326 /896 ( 36%) 110/256 ( 43%) 42 /116 ( 36%) 289/640 ( 45%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 28 28 | I/O : 41 71
Output : 3 3 | GCK/IO : 1 3
Bidirectional : 10 10 |
GCK : 1 1 |
---- ----
Total 42 42
MACROCELL RESOURCES:
Total Macrocells Available 256
Registered Macrocells 110
Non-registered Macrocell driving I/O 1
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK0.
Universal Control Terms (Used/Total) : 3/4
BLOCK RESOURCES:
Total Function Block Local Control Terms (Used/Total) : 3/128
Total Foldback NANDs (Used/Total) : 0/128
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin Reg Init
Name Pt Used Rate # Type Use State
N_PZ_559 1 4 FB1_15 (b) (b)
N_PZ_560 1 4 FB1_11 (b) (b)
N_PZ_564 1 4 FB1_10 (b) (b)
N_PZ_641 2 3 FB9_6 (b) (b)
N_PZ_662 2 3 FB9_16 139 I/O (b)
N_PZ_667 3 3 FB4_2 116 I/O I
N_PZ_668 3 5 FB9_8 (b) (b)
N_PZ_683 4 7 FB9_7 (b) (b)
data_bus<0> 6 13 FB1_14 FAST 99 I/O I/O RESET
data_bus<1> 6 13 FB2_2 FAST 108 I/O I/O RESET
data_bus<2> 7 14 FB6_2 FAST 55 I/O I/O RESET
data_bus<3> 6 13 FB2_5 FAST 109 I/O I/O RESET
data_bus<4> 7 14 FB6_3 FAST 56 I/O I/O RESET
data_bus<5> 7 14 FB1_13 FAST 100 I/O I/O RESET
data_bus<6> 7 14 FB6_5 FAST 60 I/O I/O RESET
data_bus<7> 7 14 FB6_12 FAST 61 I/O I/O RESET
dtack 3 3 FB2_1 FAST 107 I/O O RESET
i2c_ctrl__n0073 2 4 FB3_4 94 I/O I
i2c_ctrl__n0096 3 5 FB9_15 140 I/O (b)
i2c_ctrl__n0153 3 5 FB4_13 120 I/O I RESET
i2c_ctrl__n0159 5 9 FB3_16 (b) (b) RESET
i2c_ctrl__n0170 5 9 FB4_8 (b) (b)
i2c_ctrl__n0171 2 6 FB10_1 4 TDI/I/O (b)
i2c_ctrl_arb_lost 4 6 FB4_12 119 I/O I RESET
i2c_ctrl_bit_cnt<0> 5 5 FB3_15 90 I/O I RESET
i2c_ctrl_bit_cnt<1> 5 7 FB3_11 (b) (b) RESET
i2c_ctrl_bit_cnt<2> 5 8 FB3_13 (b) (b) RESET
i2c_ctrl_bus_busy 3 2 FB4_9 (b) (b) RESET
i2c_ctrl_bus_busy_d1
2 1 FB2_9 (b) (b) RESET
i2c_ctrl_clk_cnt<0> 5 10 FB4_4 (b) (b) RESET
i2c_ctrl_clk_cnt<1> 3 3 FB7_9 (b) (b) RESET
i2c_ctrl_clk_cnt<2> 6 10 FB4_16 122 I/O (b) RESET
i2c_ctrl_detect_stop
3 4 FB9_4 (b) (b) RESET
i2c_ctrl_gen_start 3 4 FB4_11 (b) (b) RESET
i2c_ctrl_gen_stop 3 5 FB4_10 (b) (b) RESET
i2c_ctrl_i2c_header<0>
4 3 FB5_7 (b) (b) RESET
i2c_ctrl_i2c_header<1>
4 3 FB5_6 (b) (b) RESET
i2c_ctrl_i2c_header<2>
4 3 FB5_16 (b) (b) RESET
i2c_ctrl_i2c_header<3>
4 3 FB5_13 (b) (b) RESET
i2c_ctrl_i2c_header<4>
4 3 FB5_11 (b) (b) RESET
i2c_ctrl_i2c_header<5>
4 3 FB5_10 (b) (b) RESET
i2c_ctrl_i2c_header<6>
4 3 FB5_9 (b) (b) RESET
i2c_ctrl_i2c_header<7>
4 3 FB5_8 (b) (b) RESET
i2c_ctrl_i2c_header_en
3 4 FB3_5 93 I/O I RESET
i2c_ctrl_maas 4 7 FB5_5 86 I/O (b) RESET
i2c_ctrl_mal 3 2 FB7_11 (b) (b) RESET
i2c_ctrl_master_sda 4 6 FB5_14 83 I/O (b) RESET
i2c_ctrl_master_slave
3 2 FB1_9 (b) (b) RESET
i2c_ctrl_mbdr_i2c<0>
3 4 FB5_3 88 I/O (b) RESET
i2c_ctrl_mbdr_i2c<1>
3 3 FB7_8 (b) (b) RESET
i2c_ctrl_mbdr_i2c<2>
3 3 FB7_7 (b) (b) RESET
i2c_ctrl_mbdr_i2c<3>
3 3 FB7_6 (b) (b) RESET
i2c_ctrl_mbdr_i2c<4>
3 3 FB7_2 (b) (b) RESET
i2c_ctrl_mbdr_i2c<5>
3 3 FB7_15 74 I/O I RESET
i2c_ctrl_mbdr_i2c<6>
3 3 FB7_14 75 I/O I RESET
i2c_ctrl_mbdr_i2c<7>
3 4 FB5_4 87 I/O (b) RESET
i2c_ctrl_mif 3 2 FB7_10 (b) (b) RESET
i2c_ctrl_msta_d1 2 1 FB4_15 (b) (b) RESET
i2c_ctrl_msta_rst 5 7 FB4_5 118 I/O I RESET
i2c_ctrl_rxak 3 2 FB9_9 (b) (b) RESET
i2c_ctrl_scl_in 2 1 FB7_16 (b) (b) RESET
i2c_ctrl_scl_out_reg
3 3 FB4_3 117 I/O I RESET
i2c_ctrl_scl_state_fft1
5 11 FB4_6 (b) (b) RESET
i2c_ctrl_scl_state_fft2
5 14 FB3_12 92 I/O I RESET
i2c_ctrl_scl_state_fft3
9 13 FB3_14 91 I/O I RESET
i2c_ctrl_sda_out_reg
13 14 FB4_7 (b) (b) RESET
i2c_ctrl_sda_out_reg_d1
2 1 FB7_13 (b) (b) RESET
i2c_ctrl_shift_out 5 5 FB9_12 (b) (b) RESET
i2c_ctrl_shift_reg<0>
5 5 FB9_11 (b) (b) RESET
i2c_ctrl_shift_reg<1>
5 5 FB9_10 (b) (b) RESET
i2c_ctrl_shift_reg<2>
5 5 FB7_12 77 I/O I RESET
i2c_ctrl_shift_reg<3>
5 5 FB7_5 78 I/O I RESET
i2c_ctrl_shift_reg<4>
5 5 FB7_4 79 I/O I RESET
i2c_ctrl_shift_reg<5>
5 5 FB7_3 80 I/O I RESET
i2c_ctrl_shift_reg<6>
5 5 FB7_1 81 I/O I RESET
i2c_ctrl_shift_reg_en
3 5 FB5_15 82 I/O (b) RESET
i2c_ctrl_shift_reg_ld
6 7 FB3_6 (b) (b) RESET
i2c_ctrl_slave_sda 4 7 FB5_12 84 I/O (b) RESET
i2c_ctrl_sm_stop 5 10 FB3_7 (b) (b) RESET
i2c_ctrl_srw 3 5 FB5_2 (b) (b) RESET
i2c_ctrl_state_ffd1 7 11 FB3_8 (b) (b) RESET
i2c_ctrl_state_ffd2 7 17 FB3_9 (b) (b) RESET
i2c_ctrl_state_ffd3 6 10 FB3_10 (b) (b) RESET
i2c_ctrl_stop_scl_reg
5 8 FB4_14 121 I/O (b) RESET
irq 1 2 FB9_1 FAST 2 I/O O
mcf 3 4 FB3_1 FAST 98 I/O O RESET
n7280 14 14 FB5_1 89 TCK/I/O (b)
scl 3 3 FB1_1 FAST 106 I/O I/O RESET
sda 2 1 FB1_4 FAST 103 I/O I/O RESET
uc_ctrl_addr_en 2 10 FB8_15 (b) (b) RESET
uc_ctrl_address_match
2 19 FB2_10 (b) (b) RESET
uc_ctrl_as_int 1 1 FB1_5 102 I/O I RESET
uc_ctrl_as_int_d1 2 2 FB8_9 (b) (b) RESET
uc_ctrl_cntrl_en 2 10 FB8_13 (b) (b) RESET
uc_ctrl_data_en 2 10 FB8_11 (b) (b) RESET
uc_ctrl_ds_int 5 8 FB1_12 101 I/O I RESET
uc_ctrl_madr<0> 2 3 FB8_8 (b) (b) RESET
uc_ctrl_madr<1> 3 4 FB8_7 (b) (b) RESET
uc_ctrl_madr<2> 3 4 FB6_15 (b) (b) RESET
uc_ctrl_madr<3> 3 4 FB8_6 (b) (b) RESET
uc_ctrl_madr<4> 3 4 FB6_11 (b) (b) RESET
uc_ctrl_madr<5> 3 4 FB1_2 (b) (b) RESET
uc_ctrl_madr<6> 3 4 FB6_10 (b) (b) RESET
uc_ctrl_madr<7> 3 4 FB6_9 (b) (b) RESET
uc_ctrl_mal_bit_reset
4 7 FB1_3 104 TDO/I/O (b) RESET
uc_ctrl_mbcr_wr 4 5 FB1_8 (b) (b) RESET
uc_ctrl_mbdr_micro<0>
3 4 FB8_14 71 I/O (b) RESET
uc_ctrl_mbdr_micro<1>
3 4 FB8_5 (b) (b) RESET
uc_ctrl_mbdr_micro<2>
3 4 FB8_12 70 I/O (b) RESET
uc_ctrl_mbdr_micro<3>
3 4 FB8_16 72 I/O (b) RESET
uc_ctrl_mbdr_micro<4>
3 4 FB8_4 69 I/O (b) RESET
uc_ctrl_mbdr_micro<5>
3 4 FB8_3 68 I/O (b) RESET
uc_ctrl_mbdr_micro<6>
3 4 FB8_2 67 I/O (b) RESET
uc_ctrl_mbdr_micro<7>
3 4 FB8_1 66 I/O (b) RESET
uc_ctrl_men 3 4 FB6_8 (b) (b) RESET
uc_ctrl_mien 3 4 FB6_7 (b) (b) RESET
uc_ctrl_mif_bit_reset
4 7 FB1_16 (b) (b) RESET
uc_ctrl_msta 3 5 FB1_6 (b) (b) RESET
uc_ctrl_mtx 3 4 FB1_7 (b) (b) RESET
uc_ctrl_prs_state_fft1
4 6 FB2_11 (b) (b) RESET
uc_ctrl_prs_state_fft2
3 6 FB2_14 (b) (b) RESET
uc_ctrl_rsta 5 7 FB6_6 (b) (b) RESET
uc_ctrl_stat_en 2 10 FB8_10 (b) (b) RESET
uc_ctrl_txak 3 4 FB9_3 (b) (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin I/O
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