light.rpt

这个是vhdl的彩灯实例程序

-- synthesized logic cell 
_LC3_B1  = LCELL( _EQ095);
  _EQ095 =  _LC8_B20 &  s4
         # !_LC7_B14 &  _LC8_B20
         #  _LC1_B1 &  s4
         #  _LC1_B1 & !_LC7_B14;

-- Node name is '~2047~2' 
-- Equation name is '~2047~2', location is LC6_B7, type is buried.
-- synthesized logic cell 
_LC6_B7  = LCELL( _EQ096);
  _EQ096 =  _LC3_B1 & !_LC6_B12 & !_LC6_B20
         #  _LC1_B1 &  _LC3_B1 & !_LC6_B12;

-- Node name is ':2062' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = LCELL( _EQ097);
  _EQ097 = !_LC5_B12 &  _LC5_B18 &  _LC8_B7
         #  _LC3_B9 &  _LC5_B18;

-- Node name is ':2071' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ098);
  _EQ098 = !_LC4_B20 &  _LC6_B9
         #  _LC2_B1 & !_LC4_B20
         #  _LC1_B12 & !_LC4_B20;

-- Node name is ':2081' 
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ099);
  _EQ099 =  _LC4_B9 & !_LC6_B10
         #  _LC1_B9 &  _LC4_B9
         #  _LC4_B1;

-- Node name is ':2119' 
-- Equation name is '_LC5_B7', type is buried 
_LC5_B7  = LCELL( _EQ100);
  _EQ100 =  _LC1_B1 &  _LC2_B7 & !_LC4_B7
         #  _LC2_B7 & !_LC4_B7 &  _LC7_B20;

-- Node name is ':2144' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = LCELL( _EQ101);
  _EQ101 = !_LC3_B23 &  _LC8_B11
         #  _LC5_B7 &  _LC8_B11
         #  _LC5_B12;

-- Node name is '~2146~1' 
-- Equation name is '~2146~1', location is LC8_B11, type is buried.
-- synthesized logic cell 
_LC8_B11 = LCELL( _EQ102);
  _EQ102 = !_LC2_B12 &  _LC3_B1 &  _LC5_B23 & !_LC6_B12;

-- Node name is ':2162' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ103);
  _EQ103 =  _LC5_B9
         #  _LC3_B7 & !_LC3_B9 &  _LC5_B18;

-- Node name is ':2176' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ104);
  _EQ104 = !_LC3_B20 &  _LC4_B5 & !_LC7_B9
         #  _LC2_B20 & !_LC7_B9;

-- Node name is ':2180' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ105);
  _EQ105 = !_LC4_B1 &  _LC5_B5
         # !_LC4_B1 &  _LC5_B1
         #  _LC8_B1;

-- Node name is ':2216' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ106);
  _EQ106 =  _LC7_B23
         # !_LC7_B20 &  _LC8_B9;

-- Node name is ':2240' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ107);
  _EQ107 =  _LC5_B12
         #  _LC1_B10 & !_LC1_B23 &  _LC8_B11;

-- Node name is '~2242~1' 
-- Equation name is '~2242~1', location is LC5_B23, type is buried.
-- synthesized logic cell 
_LC5_B23 = LCELL( _EQ108);
  _EQ108 =  _LC1_B1
         # !_LC6_B20 & !_LC8_B23;

-- Node name is '~2242~2' 
-- Equation name is '~2242~2', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ109);
  _EQ109 = !_LC2_B12 & !_LC6_B12;

-- Node name is ':2252' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = LCELL( _EQ110);
  _EQ110 =  _LC2_B1
         #  _LC2_B10 & !_LC3_B9 &  _LC5_B18;

-- Node name is '~2254~1' 
-- Equation name is '~2254~1', location is LC5_B18, type is buried.
-- synthesized logic cell 
_LC5_B18 = LCELL( _EQ111);
  _EQ111 = !_LC1_B18 & !_LC7_B1;

-- Node name is ':2266' 
-- Equation name is '_LC4_B10', type is buried 
_LC4_B10 = LCELL( _EQ112);
  _EQ112 = !_LC3_B20 &  _LC4_B20
         #  _LC3_B10 & !_LC3_B20 & !_LC6_B9;

-- Node name is ':2273' 
-- Equation name is '_LC8_B10', type is buried 
_LC8_B10 = LCELL( _EQ113);
  _EQ113 =  _LC4_B1
         #  _LC2_B20 &  _LC4_B9
         #  _LC4_B9 &  _LC4_B10;

-- Node name is '~2275~1' 
-- Equation name is '~2275~1', location is LC4_B9, type is buried.
-- synthesized logic cell 
_LC4_B9  = LCELL( _EQ114);
  _EQ114 = !_LC5_B1 & !_LC7_B9;

-- Node name is '~2357~1' 
-- Equation name is '~2357~1', location is LC2_B17, type is buried.
-- synthesized logic cell 
!_LC2_B17 = _LC2_B17~NOT;
_LC2_B17~NOT = LCELL( _EQ115);
  _EQ115 =  _LC1_B17 & !_LC2_B13;

-- Node name is '~2366~1' 
-- Equation name is '~2366~1', location is LC5_B13, type is buried.
-- synthesized logic cell 
_LC5_B13 = LCELL( _EQ116);
  _EQ116 = !flag2
         # !flag1
         #  flag0;

-- Node name is '~2375~1' 
-- Equation name is '~2375~1', location is LC3_B14, type is buried.
-- synthesized logic cell 
_LC3_B14 = LCELL( _EQ117);
  _EQ117 =  _LC2_B13 & !_LC7_B14
         #  _LC3_B19;

-- Node name is '~2393~1' 
-- Equation name is '~2393~1', location is LC1_B14, type is buried.
-- synthesized logic cell 
_LC1_B14 = LCELL( _EQ118);
  _EQ118 =  _LC2_B13 & !_LC5_B20
         #  _LC3_B19;

-- Node name is '~2411~1' 
-- Equation name is '~2411~1', location is LC5_B19, type is buried.
-- synthesized logic cell 
_LC5_B19 = LCELL( _EQ119);
  _EQ119 =  _LC2_B13 & !s0
         #  _LC2_B13 & !s1
         #  _LC3_B19;

-- Node name is '~2429~1' 
-- Equation name is '~2429~1', location is LC4_B19, type is buried.
-- synthesized logic cell 
_LC4_B19 = LCELL( _EQ120);
  _EQ120 =  _LC3_B19
         #  _LC2_B13 & !s0;

-- Node name is '~2447~1' 
-- Equation name is '~2447~1', location is LC3_B19, type is buried.
-- synthesized logic cell 
_LC3_B19 = LCELL( _EQ121);
  _EQ121 = !_LC2_B13 &  _LC5_B13
         # !_LC1_B17;

-- Node name is ':2459' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = LCELL( _EQ122);
  _EQ122 =  _LC2_B13 &  _LC7_B2
         # !_LC2_B13 & !_LC3_B13 &  _LC6_B2;

-- Node name is '~2461~1' 
-- Equation name is '~2461~1', location is LC2_B6, type is buried.
-- synthesized logic cell 
_LC2_B6  = LCELL( _EQ123);
  _EQ123 = !_LC2_B13 & !_LC3_B13;

-- Node name is ':2477' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ124);
  _EQ124 =  _LC1_B3 &  _LC2_B2
         #  _LC2_B6 &  _LC4_B2;

-- Node name is '~2478~1' 
-- Equation name is '~2478~1', location is LC1_B3, type is buried.
-- synthesized logic cell 
_LC1_B3  = LCELL( _EQ125);
  _EQ125 =  _LC2_B13 & !_LC8_B1;

-- Node name is ':2480' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ126);
  _EQ126 =  _LC3_B2 & !_LC4_B13
         #  _LC2_B3 &  _LC4_B13;

-- Node name is ':2495' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = LCELL( _EQ127);
  _EQ127 =  _LC2_B13 &  _LC6_B3
         #  _LC2_B3 &  _LC2_B6;

-- Node name is ':2498' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ128);
  _EQ128 = !_LC4_B13 &  _LC7_B3
         #  _LC4_B8 &  _LC4_B13;

-- Node name is ':2513' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = LCELL( _EQ129);
  _EQ129 =  _LC1_B3 &  _LC3_B8
         #  _LC2_B6 &  _LC4_B8;

-- Node name is ':2516' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = LCELL( _EQ130);
  _EQ130 = !_LC4_B13 &  _LC5_B8
         #  _LC4_B13 &  _LC7_B8;

-- Node name is ':2531' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ131);
  _EQ131 =  _LC2_B13 &  _LC7_B6
         #  _LC2_B6 &  _LC7_B8;

-- Node name is ':2534' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = LCELL( _EQ132);
  _EQ132 = !_LC4_B13 &  _LC8_B6
         #  _LC4_B13 &  _LC8_B8;

-- Node name is ':2549' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = LCELL( _EQ133);
  _EQ133 =  _LC1_B3 &  _LC2_B9
         #  _LC2_B6 &  _LC8_B8;

-- Node name is ':2552' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = LCELL( _EQ134);
  _EQ134 =  _LC1_B8 & !_LC4_B13
         #  _LC3_B5 &  _LC4_B13;

-- Node name is ':2567' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ135);
  _EQ135 =  _LC2_B13 &  _LC6_B5
         #  _LC2_B6 &  _LC3_B5;

-- Node name is ':2570' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ136);
  _EQ136 = !_LC4_B13 &  _LC7_B5
         #  _LC1_B5 &  _LC4_B13;

-- Node name is ':2585' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ137);
  _EQ137 =  _LC1_B3 &  _LC8_B10
         #  _LC1_B5 &  _LC2_B6;

-- Node name is '~2611~1' 
-- Equation name is '~2611~1', location is LC1_B17, type is buried.
-- synthesized logic cell 
_LC1_B17 = LCELL( _EQ138);
  _EQ138 = !_LC4_B13 & !_LC8_B13;

-- Node name is ':2640' 
-- Equation name is '_LC5_B14', type is buried 
_LC5_B14 = LCELL( _EQ139);
  _EQ139 =  _LC2_B13 &  _LC7_B14 &  s4;

-- Node name is ':2643' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = LCELL( _EQ140);
  _EQ140 =  _LC4_B2 &  _LC4_B13;

-- Node name is ':2644' 
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = LCELL( _EQ141);
  _EQ141 =  flag0 & !_LC3_B13 & !_LC4_B13
         # !_LC4_B13 &  _LC5_B14;

-- Node name is ':2788' 
-- Equation name is '_LC5_B22', type is buried 
_LC5_B22 = LCELL( _EQ142);
  _EQ142 =  banner &  clk1
         # !banner &  clk2;



Project Information             d:\08asic\experiment\no_2_colorlight\light.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,907K