📄 light.rpt
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- 2 - B 09 OR2 0 4 0 1 :2081
- 5 - B 07 OR2 0 4 0 1 :2119
- 3 - B 07 OR2 0 4 0 1 :2144
- 8 - B 11 AND2 s 0 4 0 2 ~2146~1
- 4 - B 05 OR2 0 4 0 1 :2162
- 5 - B 05 OR2 0 4 0 1 :2176
- 6 - B 05 OR2 0 4 0 1 :2180
- 1 - B 10 OR2 0 3 0 1 :2216
- 2 - B 10 OR2 0 4 0 1 :2240
- 5 - B 23 OR2 s 0 3 0 4 ~2242~1
- 8 - B 12 AND2 s 0 2 0 1 ~2242~2
- 3 - B 10 OR2 0 4 0 1 :2252
- 5 - B 18 AND2 s 0 2 0 4 ~2254~1
- 4 - B 10 OR2 0 4 0 1 :2266
- 8 - B 10 OR2 0 4 0 1 :2273
- 4 - B 09 AND2 s 0 2 0 4 ~2275~1
- 2 - B 17 AND2 s ! 0 2 0 1 ~2357~1
- 5 - B 13 OR2 s 0 3 0 2 ~2366~1
- 3 - B 14 OR2 s 0 3 0 1 ~2375~1
- 1 - B 14 OR2 s 0 3 0 1 ~2393~1
- 5 - B 19 OR2 s 0 4 0 1 ~2411~1
- 4 - B 19 OR2 s 0 3 0 1 ~2429~1
- 3 - B 19 OR2 s 0 3 0 5 ~2447~1
- 8 - B 02 OR2 0 4 0 1 :2459
- 2 - B 06 AND2 s 0 2 0 7 ~2461~1
- 3 - B 02 OR2 0 4 0 1 :2477
- 1 - B 03 AND2 s 0 2 0 4 ~2478~1
- 5 - B 02 OR2 0 3 0 1 :2480
- 7 - B 03 OR2 0 4 0 1 :2495
- 8 - B 03 OR2 0 3 0 1 :2498
- 5 - B 08 OR2 0 4 0 1 :2513
- 6 - B 08 OR2 0 3 0 1 :2516
- 8 - B 06 OR2 0 4 0 1 :2531
- 4 - B 06 OR2 0 3 0 1 :2534
- 1 - B 08 OR2 0 4 0 1 :2549
- 2 - B 08 OR2 0 3 0 1 :2552
- 7 - B 05 OR2 0 4 0 1 :2567
- 8 - B 05 OR2 0 3 0 1 :2570
- 2 - B 05 OR2 0 4 0 1 :2585
- 1 - B 17 AND2 s 0 2 0 4 ~2611~1
- 5 - B 14 AND2 0 3 0 1 :2640
- 1 - B 02 AND2 0 2 0 1 :2643
- 8 - B 14 OR2 0 4 0 1 :2644
- 5 - B 22 OR2 1 2 0 17 :2788
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\08asic\experiment\no_2_colorlight\light.rpt
light
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 40/ 96( 41%) 40/ 48( 83%) 19/ 48( 39%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\08asic\experiment\no_2_colorlight\light.rpt
light
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 17 :2788
INPUT 2 clk1
Device-Specific Information: d:\08asic\experiment\no_2_colorlight\light.rpt
light
** EQUATIONS **
clk1 : INPUT;
-- Node name is ':25' = 'banner'
-- Equation name is 'banner', location is LC1_B22, type is buried.
banner = DFFE( _EQ001, _LC5_B22, VCC, VCC, VCC);
_EQ001 = banner & _LC2_B13
# banner & !_LC1_B17
# banner & _LC5_B13
# !banner & _LC1_B17 & !_LC2_B13 & !_LC5_B13;
-- Node name is ':18' = 'clk2'
-- Equation name is 'clk2', location is LC2_B22, type is buried.
clk2 = DFFE(!clk2, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':47' = 'flag0'
-- Equation name is 'flag0', location is LC4_B14, type is buried.
flag0 = DFFE( _EQ002, _LC5_B22, VCC, VCC, VCC);
_EQ002 = !_LC8_B13 & _LC8_B14
# _LC1_B2 & !_LC8_B13
# _LC3_B5 & _LC8_B13;
-- Node name is ':46' = 'flag1'
-- Equation name is 'flag1', location is LC1_B13, type is buried.
flag1 = DFFE( _EQ003, _LC5_B22, VCC, VCC, VCC);
_EQ003 = flag0 & !flag2 & !_LC4_B2
# flag0 & flag1
# flag1 & !flag2;
-- Node name is ':45' = 'flag2'
-- Equation name is 'flag2', location is LC7_B13, type is buried.
flag2 = DFFE( _EQ004, _LC5_B22, VCC, VCC, VCC);
_EQ004 = !_LC2_B17 & _LC3_B13
# flag2 & !_LC2_B17 & !_LC6_B13;
-- Node name is 'light0'
-- Equation name is 'light0', type is output
light0 = _LC1_B5;
-- Node name is 'light1'
-- Equation name is 'light1', type is output
light1 = _LC3_B5;
-- Node name is 'light2'
-- Equation name is 'light2', type is output
light2 = _LC8_B8;
-- Node name is 'light3'
-- Equation name is 'light3', type is output
light3 = _LC7_B8;
-- Node name is 'light4'
-- Equation name is 'light4', type is output
light4 = _LC4_B8;
-- Node name is 'light5'
-- Equation name is 'light5', type is output
light5 = _LC2_B3;
-- Node name is 'light6'
-- Equation name is 'light6', type is output
light6 = _LC4_B2;
-- Node name is 'light7'
-- Equation name is 'light7', type is output
light7 = _LC6_B2;
-- Node name is ':24' = 's0'
-- Equation name is 's0', location is LC8_B19, type is buried.
s0 = DFFE( _EQ005, _LC5_B22, VCC, VCC, VCC);
_EQ005 = _LC3_B19 & s0
# _LC7_B19 & !s0;
-- Node name is ':23' = 's1'
-- Equation name is 's1', location is LC1_B19, type is buried.
s1 = DFFE( _EQ006, _LC5_B22, VCC, VCC, VCC);
_EQ006 = _LC4_B19 & s1
# _LC7_B19 & s0 & !s1;
-- Node name is ':22' = 's2'
-- Equation name is 's2', location is LC6_B19, type is buried.
s2 = DFFE( _EQ007, _LC5_B22, VCC, VCC, VCC);
_EQ007 = _LC2_B19 & _LC7_B19
# _LC5_B19 & s2;
-- Node name is ':21' = 's3'
-- Equation name is 's3', location is LC2_B14, type is buried.
s3 = DFFE( _EQ008, _LC5_B22, VCC, VCC, VCC);
_EQ008 = _LC5_B20 & _LC7_B19 & !s3
# _LC1_B14 & s3;
-- Node name is ':20' = 's4'
-- Equation name is 's4', location is LC6_B14, type is buried.
s4 = DFFE( _EQ009, _LC5_B22, VCC, VCC, VCC);
_EQ009 = _LC3_B14 & s4
# _LC7_B14 & _LC7_B19 & !s4;
-- Node name is '|LPM_ADD_SUB:612|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B20', type is buried
!_LC5_B20 = _LC5_B20~NOT;
_LC5_B20~NOT = LCELL( _EQ010);
_EQ010 = !s2
# !s0
# !s1;
-- Node name is '|LPM_ADD_SUB:612|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ011);
_EQ011 = _LC5_B20 & s3;
-- Node name is ':2'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = DFFE( _EQ012, _LC5_B22, VCC, VCC, VCC);
_EQ012 = !_LC4_B13 & _LC8_B2
# _LC4_B2 & _LC4_B13
# _LC8_B13;
-- Node name is ':4'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( _EQ013, _LC5_B22, VCC, VCC, VCC);
_EQ013 = _LC5_B2 & !_LC8_B13
# _LC6_B2 & _LC8_B13;
-- Node name is ':6'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _EQ014, _LC5_B22, VCC, VCC, VCC);
_EQ014 = _LC8_B3 & !_LC8_B13
# _LC4_B2 & _LC8_B13;
-- Node name is ':8'
-- Equation name is '_LC4_B8', type is buried
_LC4_B8 = DFFE( _EQ015, _LC5_B22, VCC, VCC, VCC);
_EQ015 = _LC6_B8 & !_LC8_B13
# _LC2_B3 & _LC8_B13;
-- Node name is ':10'
-- Equation name is '_LC7_B8', type is buried
_LC7_B8 = DFFE( _EQ016, _LC5_B22, VCC, VCC, VCC);
_EQ016 = _LC4_B6 & !_LC8_B13
# _LC4_B8 & _LC8_B13;
-- Node name is ':12'
-- Equation name is '_LC8_B8', type is buried
_LC8_B8 = DFFE( _EQ017, _LC5_B22, VCC, VCC, VCC);
_EQ017 = _LC2_B8 & !_LC8_B13
# _LC7_B8 & _LC8_B13;
-- Node name is ':14'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = DFFE( _EQ018, _LC5_B22, VCC, VCC, VCC);
_EQ018 = _LC8_B5 & !_LC8_B13
# _LC8_B8 & _LC8_B13;
-- Node name is ':16'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = DFFE( _EQ019, _LC5_B22, VCC, VCC, VCC);
_EQ019 = _LC3_B5 & _LC8_B13
# _LC2_B5 & !_LC4_B13 & !_LC8_B13;
-- Node name is '~346~1'
-- Equation name is '~346~1', location is LC7_B19, type is buried.
-- synthesized logic cell
_LC7_B19 = LCELL( _EQ020);
_EQ020 = _LC1_B17 & _LC2_B13;
-- Node name is ':346'
-- Equation name is '_LC8_B13', type is buried
!_LC8_B13 = _LC8_B13~NOT;
_LC8_B13~NOT = LCELL( _EQ021);
_EQ021 = flag0
# flag1
# flag2;
-- Node name is ':350'
-- Equation name is '_LC4_B13', type is buried
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ022);
_EQ022 = flag1
# !flag0
# flag2;
-- Node name is '~354~1'
-- Equation name is '~354~1', location is LC6_B13, type is buried.
-- synthesized logic cell
!_LC6_B13 = _LC6_B13~NOT;
_LC6_B13~NOT = LCELL( _EQ023);
_EQ023 = !flag1
# flag0;
-- Node name is ':354'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ024);
_EQ024 = !flag0 & flag1 & !flag2;
-- Node name is ':358'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ025);
_EQ025 = flag0 & flag1 & !flag2;
-- Node name is '~1223~1'
-- Equation name is '~1223~1', location is LC2_B19, type is buried.
-- synthesized logic cell
_LC2_B19 = LCELL( _EQ026);
_EQ026 = s0 & s1 & !s2;
-- Node name is '~1223~2'
-- Equation name is '~1223~2', location is LC8_B9, type is buried.
-- synthesized logic cell
_LC8_B9 = LCELL( _EQ027);
_EQ027 = s3 & s4;
-- Node name is '~1251~1'
-- Equation name is '~1251~1', location is LC6_B20, type is buried.
-- synthesized logic cell
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = LCELL( _EQ028);
_EQ028 = !s0
# s1
# s2;
-- Node name is ':1254'
-- Equation name is '_LC2_B21', type is buried
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ029);
_EQ029 = !_LC8_B9
# !_LC6_B20 & !_LC8_B23;
-- Node name is '~1265~1'
-- Equation name is '~1265~1', location is LC8_B20, type is buried.
-- synthesized logic cell
_LC8_B20 = LCELL( _EQ030);
_EQ030 = s0
# s1
# s2;
-- Node name is ':1265'
-- Equation name is '_LC8_B16', type is buried
!_LC8_B16 = _LC8_B16~NOT;
_LC8_B16~NOT = LCELL( _EQ031);
_EQ031 = _LC8_B20
# !_LC8_B9;
-- Node name is ':1307'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ032);
_EQ032 = !_LC1_B1 & s0 & !s1 & s2;
-- Node name is ':1321'
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = LCELL( _EQ033);
_EQ033 = !_LC1_B1 & !s0 & !s1 & s2;
-- Node name is '~1335~1'
-- Equation name is '~1335~1', location is LC1_B1, type is buried.
-- synthesized logic cell
!_LC1_B1 = _LC1_B1~NOT;
_LC1_B1~NOT = LCELL( _EQ034);
_EQ034 = !s3 & s4;
-- Node name is ':1335'
-- Equation name is '_LC1_B23', type is buried
!_LC1_B23 = _LC1_B23~NOT;
_LC1_B23~NOT = LCELL( _EQ035);
_EQ035 = _LC1_B1
# !_LC2_B19;
-- Node name is '~1382~1'
-- Equation name is '~1382~1', location is LC5_B11, type is buried.
-- synthesized logic cell
_LC5_B11 = LCELL( _EQ036);
_EQ036 = !_LC2_B11 & _LC3_B23 & _LC5_B23;
-- Node name is ':1382'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ037);
_EQ037 = _LC2_B21 & _LC5_B11 & _LC8_B20
# _LC2_B21 & _LC5_B11 & !_LC8_B9;
-- Node name is ':1405'
-- Equation name is '_LC6_B12', type is buried
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