ufm.v

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核

// megafunction wizard: %Flash Memory%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altufm 

// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// 			altufm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Internal Build 142b 11/01/2004 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.


//altufm_parallel ACCESS_MODE="READ_ONLY" CBX_AUTO_BLACKBOX="ON" DEVICE_FAMILY="MAX II" LPM_FILE="TEST.MIF" OSC_FREQUENCY=136000 WIDTH_ADDRESS=9 WIDTH_DATA=16 WIDTH_UFM_ADDRESS=9 addr data_valid di do nbusy nread osc
//VERSION_BEGIN 4.2cb cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:07:21:16:27:34:SJ cbx_altufm 2004:11:01:17:59:18:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2004:10:26:14:09:44:SJ cbx_lpm_compare 2004:10:26:14:09:48:SJ cbx_lpm_counter 2004:10:26:14:10:24:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_maxii 2004:10:26:14:10:22:SJ cbx_mgl 2004:10:26:14:10:52:SJ cbx_stratix 2004:10:26:14:10:20:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:10:26:14:57:38:SJ  VERSION_END


//lpm_counter CBX_AUTO_BLACKBOX="ON" DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_modulus=28 lpm_width=5 clk_en clock q
//VERSION_BEGIN 4.2cb cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:26:14:09:44:SJ cbx_lpm_compare 2004:10:26:14:09:48:SJ cbx_lpm_counter 2004:10:26:14:10:24:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_mgl 2004:10:26:14:10:52:SJ cbx_stratix 2004:10:26:14:10:20:SJ cbx_stratixii 2004:08:10:15:01:36:SJ  VERSION_END

//synthesis_resources = lut 48 maxii_ufm 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  UFM_altufm_parallel_pej
	( 
	addr,
	data_valid,
	di,
	do,
	nbusy,
	nread,
	osc) /* synthesis synthesis_clearbox=1 */;
	input   [8:0]  addr;
	output   data_valid;
	input   [15:0]  di;
	output   [15:0]  do;
	output   nbusy;
	input   nread;
	output   osc;

	wire	[15:0]	wire_dffe10a_D;
	reg	[15:0]	dffe10a;
	wire	[15:0]	wire_dffe10a_ENA;
	reg	dffe11;
	reg	dffe12;
	reg	dffe2;
	reg	dffe3;
	reg	dffe4;
	reg	dffe6;
	reg	dffe7;
	wire	[8:0]	wire_dffe8a_D;
	reg	[8:0]	dffe8a;
	reg	[0:0]	dffe9a0;
	reg	[0:0]	dffe9a1;
	reg	[0:0]	dffe9a2;
	reg	[0:0]	dffe9a3;
	reg	[0:0]	dffe9a4;
	reg	[0:0]	dffe9a5;
	reg	[0:0]	dffe9a6;
	reg	[0:0]	dffe9a7;
	reg	[0:0]	dffe9a8;
	reg	[0:0]	dffe9a9;
	reg	[0:0]	dffe9a10;
	reg	[0:0]	dffe9a11;
	reg	[0:0]	dffe9a12;
	reg	[0:0]	dffe9a13;
	reg	[0:0]	dffe9a14;
	reg	[0:0]	dffe9a15;
	reg	[5:0]	wire_cntr5_q_int;
	wire	wire_cntr5_clk_en;
	wire	wire_cntr5_clock;
	wire	[4:0]	wire_cntr5_q;
	wire  wire_maxii_ufm_block1_bgpbusy;
	wire  wire_maxii_ufm_block1_drdout;
	wire  wire_maxii_ufm_block1_osc;
	wire  add_en;
	wire  add_load;
	wire  arclk;
	wire  busy_arclk;
	wire  busy_drclk;
	wire  control_mux;
	wire  copy_tmp_decode;
	wire  data_valid_en;
	wire  dly_real_decode;
	wire  dly_tmp_decode;
	wire  drdin;
	wire  gated1;
	wire  gated2;
	wire  hold_decode;
	wire  in_read_data_en;
	wire  in_read_drclk;
	wire  in_read_drshft;
	wire  mux_nread;
	wire  q0;
	wire  q1;
	wire  q2;
	wire  q3;
	wire  q4;
	wire  read;
	wire  read_op;
	wire  real_decode;
	wire  [8:0]  shiftin;
	wire  [15:0]  sipo_q;
	wire  start_decode;
	wire  start_op;
	wire  stop_op;
	wire  tmp_add_en;
	wire  tmp_add_load;
	wire  tmp_arclk;
	wire  tmp_arclk0;
	wire  tmp_ardin;
	wire  tmp_arshft;
	wire  tmp_data_valid2;
	wire  tmp_decode;
	wire  tmp_drclk;
	wire  tmp_in_read_data_en;
	wire  tmp_in_read_drclk;
	wire  tmp_in_read_drshft;
	wire  tmp_read;
	wire  ufm_arclk;
	wire  ufm_ardin;
	wire  ufm_arshft;
	wire  ufm_bgpbusy;
	wire  ufm_drclk;
	wire  ufm_drdin;
	wire  ufm_drdout;
	wire  ufm_drshft;
	wire  ufm_osc;
	wire  ufm_oscena;
	wire  [8:0]  X_var;
	wire  [8:0]  Y_var;
	wire  [8:0]  Z_var;

	// synopsys translate_off
	initial
		dffe10a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[0:0] == 1'b1)   dffe10a[0:0] <= wire_dffe10a_D[0:0];
	// synopsys translate_off
	initial
		dffe10a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[1:1] == 1'b1)   dffe10a[1:1] <= wire_dffe10a_D[1:1];
	// synopsys translate_off
	initial
		dffe10a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[2:2] == 1'b1)   dffe10a[2:2] <= wire_dffe10a_D[2:2];
	// synopsys translate_off
	initial
		dffe10a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[3:3] == 1'b1)   dffe10a[3:3] <= wire_dffe10a_D[3:3];
	// synopsys translate_off
	initial
		dffe10a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[4:4] == 1'b1)   dffe10a[4:4] <= wire_dffe10a_D[4:4];
	// synopsys translate_off
	initial
		dffe10a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[5:5] == 1'b1)   dffe10a[5:5] <= wire_dffe10a_D[5:5];
	// synopsys translate_off
	initial
		dffe10a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[6:6] == 1'b1)   dffe10a[6:6] <= wire_dffe10a_D[6:6];
	// synopsys translate_off
	initial
		dffe10a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[7:7] == 1'b1)   dffe10a[7:7] <= wire_dffe10a_D[7:7];
	// synopsys translate_off
	initial
		dffe10a[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[8:8] == 1'b1)   dffe10a[8:8] <= wire_dffe10a_D[8:8];
	// synopsys translate_off
	initial
		dffe10a[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[9:9] == 1'b1)   dffe10a[9:9] <= wire_dffe10a_D[9:9];
	// synopsys translate_off
	initial
		dffe10a[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[10:10] == 1'b1)   dffe10a[10:10] <= wire_dffe10a_D[10:10];
	// synopsys translate_off
	initial
		dffe10a[11:11] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[11:11] == 1'b1)   dffe10a[11:11] <= wire_dffe10a_D[11:11];
	// synopsys translate_off
	initial
		dffe10a[12:12] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[12:12] == 1'b1)   dffe10a[12:12] <= wire_dffe10a_D[12:12];
	// synopsys translate_off
	initial
		dffe10a[13:13] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[13:13] == 1'b1)   dffe10a[13:13] <= wire_dffe10a_D[13:13];
	// synopsys translate_off
	initial
		dffe10a[14:14] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[14:14] == 1'b1)   dffe10a[14:14] <= wire_dffe10a_D[14:14];
	// synopsys translate_off
	initial
		dffe10a[15:15] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe10a_ENA[15:15] == 1'b1)   dffe10a[15:15] <= wire_dffe10a_D[15:15];
	assign
		wire_dffe10a_D = {sipo_q[15:0]};
	assign
		wire_dffe10a_ENA = {16{(dffe6 & (~ tmp_decode))}};
	// synopsys translate_off
	initial
		dffe11 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe11 <= busy_arclk;
	// synopsys translate_off
	initial
		dffe12 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe12 <= busy_drclk;
	// synopsys translate_off
	initial
		dffe2 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe2 <= start_decode;
	// synopsys translate_off
	initial
		dffe3 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (start_op == 1'b1)   dffe3 <= mux_nread;
	// synopsys translate_off
	initial
		dffe4 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe4 <= copy_tmp_decode;
	// synopsys translate_off
	initial
		dffe6 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (data_valid_en == 1'b1)   dffe6 <= tmp_data_valid2;
	// synopsys translate_off
	initial
		dffe7 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe7 <= (dffe6 & (~ tmp_decode));
	// synopsys translate_off
	initial
		dffe8a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe8a[0:0] <= wire_dffe8a_D[0:0];
	// synopsys translate_off
	initial
		dffe8a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe8a[1:1] <= wire_dffe8a_D[1:1];
	// synopsys translate_off
	initial
		dffe8a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe8a[2:2] <= wire_dffe8a_D[2:2];
	// synopsys translate_off
	initial
		dffe8a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe8a[3:3] <= wire_dffe8a_D[3:3];
	// synopsys translate_off
	initial
		dffe8a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe8a[4:4] <= wire_dffe8a_D[4:4];
	// synopsys translate_off