sram_interface.v

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核

module sram_interface(
	clock,
	address,
	data_in,
	data_out,
	go_read,
	go_write,
	chipselect,
	complete,
	
	sram_address,
	sram_data,
	sram_ncs,
	sram_noe,
	sram_nwe);

parameter	idle = 0;
parameter	s1 = 1;
parameter	s2 = 2;
parameter	s3 = 3;
parameter	s4 = 4;
parameter	s5 = 5;

input			clock;
input			go_read;
input			go_write;
input			chipselect;
input	[14:0]	address;
input	[15:0]	data_in;

output			complete;
output			sram_ncs;
output			sram_noe;
output			sram_nwe;
output	[15:0]	sram_address;
output	[15:0]	data_out;

inout	[7:0]	sram_data;

reg				complete;
reg		[15:0]	sram_address;

reg		[5:0]	fsm, next_state;
reg				datah_ena, datal_ena;
reg		[7:0]	datah, datal;

reg				sram_complete, sram_chipselect;
reg		[7:0]	sram_data_out;
reg		[7:0]	sram_data_in;
sram_controller	sram(.clock(clock), .data_in(sram_data_in),	.go_read(go_read), 
					.go_write(go_write), .chipselect(sram_chipselect),
					.complete(sram_complete), .data(sram_data), .noe(sram_noe),
					.nwe(sram_nwe), .ncs(sram_ncs));

assign data_out = {datah, datal};

always @ (posedge clock) begin
	fsm <= next_state;
	if(datah_ena == 1'b1)
		datah <= sram_data;
	if(datal_ena == 1'b1)
		datal <= sram_data;
end

always @ (fsm, go_read, go_write, chipselect, address, data_in, sram_complete) begin
	sram_address <= 0;
	datal_ena <= 1'b0;
	datah_ena <= 1'b0;
	complete <= 1'b0;
	sram_chipselect <= 1'b0;
	sram_data_in <= 0;
	next_state <= fsm;
	case(fsm)
		idle:begin
			sram_address <= {address, 1'b0};
			sram_data_in <= data_in[7:0];
			if(go_read  == 1'b1) begin
				sram_chipselect <= chipselect;
				if(sram_complete == 1'b1) begin
					datal_ena <= 1'b1;
					next_state <= s1;
				end
			end
			if(go_write == 1'b1) begin
				sram_chipselect <= chipselect;
				if(sram_complete == 1'b1)
					next_state <= s3;
			end
		end
		
		s1:begin
			sram_chipselect <= 1'b1;
			sram_address <= {address, 1'b1};
			if(sram_complete == 1'b1) begin
				datah_ena <= 1'b1;
				next_state <= s2;
			end
		end
		
		s2:begin
			complete <= 1'b1;
			next_state <= idle;
		end
		
		s3:begin
			sram_data_in <= data_in[15:8];
			sram_chipselect <= 1'b1;
			sram_address <= {address, 1'b1};
			if(sram_complete == 1'b1) begin
				complete <= 1'b1;
				next_state <= idle;
			end
		end
	endcase
end
endmodule