📄 tiny16_maxii.map.rpt
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; fsm.s1 ; 0 ; 1 ; 0 ; 1 ;
; fsm.s3 ; 1 ; 0 ; 0 ; 1 ;
+----------+--------+--------+--------+----------+
+-----------+
; Hierarchy ;
+-----------+
tiny16_MAXII
|-- tiny16:cpu
|-- lpm_add_sub:add_sub
|-- alt_stratix_add_sub:stratix_adder
|-- flash:flash
|-- UFM:flash
|-- UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component
|-- lcd_controller:lcd
|-- lpm_counter:count_rtl_0
|-- cntr_2q7:auto_generated
|-- sram_interface:ram
|-- sram_controller:sram
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------+
; |tiny16_MAXII ; 899 (67) ; 222 ; 1 ; 45 ; 0 ; 677 (64) ; 122 (3) ; 100 (0) ; 109 (0) ; |tiny16_MAXII ;
; |flash:flash| ; 102 (26) ; 76 ; 1 ; 0 ; 0 ; 26 (3) ; 58 (19) ; 18 (4) ; 5 (0) ; |tiny16_MAXII|flash:flash ;
; |UFM:flash| ; 76 (0) ; 53 ; 1 ; 0 ; 0 ; 23 (0) ; 39 (0) ; 14 (0) ; 5 (0) ; |tiny16_MAXII|flash:flash|UFM:flash ;
; |UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component| ; 76 (76) ; 53 ; 1 ; 0 ; 0 ; 23 (23) ; 39 (39) ; 14 (14) ; 5 (5) ; |tiny16_MAXII|flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component ;
; |lcd_controller:lcd| ; 32 (28) ; 21 ; 0 ; 0 ; 0 ; 11 (11) ; 9 (9) ; 12 (8) ; 4 (0) ; |tiny16_MAXII|lcd_controller:lcd ;
; |lpm_counter:count_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |tiny16_MAXII|lcd_controller:lcd|lpm_counter:count_rtl_0 ;
; |cntr_2q7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |tiny16_MAXII|lcd_controller:lcd|lpm_counter:count_rtl_0|cntr_2q7:auto_generated ;
; |sram_interface:ram| ; 96 (85) ; 29 ; 0 ; 0 ; 0 ; 67 (65) ; 20 (17) ; 9 (3) ; 0 (0) ; |tiny16_MAXII|sram_interface:ram ;
; |sram_controller:sram| ; 11 (11) ; 9 ; 0 ; 0 ; 0 ; 2 (2) ; 3 (3) ; 6 (6) ; 0 (0) ; |tiny16_MAXII|sram_interface:ram|sram_controller:sram ;
; |tiny16:cpu| ; 602 (584) ; 93 ; 0 ; 0 ; 0 ; 509 (491) ; 32 (32) ; 61 (61) ; 100 (82) ; |tiny16_MAXII|tiny16:cpu ;
; |lpm_add_sub:add_sub| ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 0 (0) ; 0 (0) ; 18 (0) ; |tiny16_MAXII|tiny16:cpu|lpm_add_sub:add_sub ;
; |alt_stratix_add_sub:stratix_adder| ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 18 (18) ; 0 (0) ; 0 (0) ; 18 (18) ; |tiny16_MAXII|tiny16:cpu|lpm_add_sub:add_sub|alt_stratix_add_sub:stratix_adder ;
+----------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/OtherQuartusProjects/Processor/Verilog/tiny16/tiny16_MAXII.map.eqn.
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; tiny16_MAXII.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/tiny16_MAXII.v ;
; flash.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/flash.v ;
; UFM.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/UFM.v ;
; tiny16.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/tiny16.v ;
; lpm_add_sub.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal42.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
; alt_stratix_add_sub.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.tdf ;
; stratix_lcell.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/stratix_lcell.inc ;
; sram_interface.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/sram_interface.v ;
; sram_controller.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/sram_controller.v ;
; lcd_controller.v ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/lcd_controller.v ;
; lpm_counter.tdf ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_2q7.tdf ; yes ; C:/OtherQuartusProjects/Processor/Verilog/tiny16/db/cntr_2q7.tdf ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+--------------------------------------------------------------------------------------------------------------+
; Resource ; Usage ;
+-----------------------------------+--------------------------------------------------------------------------------------------------------------+
; Logic cells ; 899 ;
; Total combinational functions ; 777 ;
; Total 4-input functions ; 568 ;
; Total 3-input functions ; 60 ;
; Total 2-input functions ; 90 ;
; Total 1-input functions ; 55 ;
; Total 0-input functions ; 4 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 222 ;
; Total logic cells in carry chains ; 109 ;
; I/O pins ; 45 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|wire_maxii_ufm_block1_drdout ;
; Maximum fan-out ; 225 ;
; Total fan-out ; 3442 ;
; Average fan-out ; 3.64 ;
+-----------------------------------+--------------------------------------------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Beta Analysis & Synthesis
Info: Version 4.2 Internal Build 142b 11/01/2004 SJ Full Version
Info: Processing started: Thu Dec 02 11:24:14 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off tiny16_MAXII -c tiny16_MAXII
Info: Found 1 design units, including 1 entities, in source file tiny16_MAXII.v
Info: Found entity 1: tiny16_MAXII
Info: Using design file flash.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: flash
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