tiny16_maxii.map.rpt

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核

Analysis & Synthesis report for tiny16_MAXII
Thu Dec 02 11:24:35 2004
Version 4.2 Internal Build 142b 11/01/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. State Machine - |tiny16_MAXII|lcd_controller:lcd|fsm
  8. State Machine - |tiny16_MAXII|sram_interface:ram|fsm
  9. State Machine - |tiny16_MAXII|sram_interface:ram|sram_controller:sram|fsm
 10. State Machine - |tiny16_MAXII|tiny16:cpu|fsm
 11. State Machine - |tiny16_MAXII|flash:flash|fsm
 12. Hierarchy
 13. Analysis & Synthesis Resource Utilization by Entity
 14. Analysis & Synthesis Equations
 15. Analysis & Synthesis Source Files Read
 16. Analysis & Synthesis Resource Usage Summary
 17. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                            ;
+-----------------------------+-----------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 02 11:24:35 2004                     ;
; Quartus II Version          ; (Beta) 4.2 Internal Build 142b 11/01/2004 SJ Full Version ;
; Revision Name               ; tiny16_MAXII                                              ;
; Top-level Entity Name       ; tiny16_MAXII                                              ;
; Family                      ; MAX II                                                    ;
; Total logic elements        ; 899                                                       ;
; Total pins                  ; 45                                                        ;
; Total virtual pins          ; 0                                                         ;
; UFM blocks                  ; 1                                                         ;
+-----------------------------+-----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                        ;
+--------------------------------------------------------------------+-----------------+---------------+
; Option                                                             ; Setting         ; Default Value ;
+--------------------------------------------------------------------+-----------------+---------------+
; Device                                                             ; EPM1270F256C5ES ;               ;
; Family name                                                        ; MAX II          ; Stratix       ;
; Use smart compilation                                              ; Normal          ; Normal        ;
; Restructure Multiplexers                                           ; Auto            ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off             ; off           ;
; Preserve fewer node names                                          ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off             ; Off           ;
; Verilog Version                                                    ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93          ; VHDL93        ;
; Top-level entity name                                              ; tiny16_MAXII    ; tiny16_MAXII  ;
; State Machine Processing                                           ; Auto            ; Auto          ;
; Extract Verilog State Machines                                     ; On              ; On            ;
; Extract VHDL State Machines                                        ; On              ; On            ;
; NOT Gate Push-Back                                                 ; On              ; On            ;
; Power-Up Don't Care                                                ; On              ; On            ;
; Remove Redundant Logic Cells                                       ; Off             ; Off           ;
; Remove Duplicate Registers                                         ; On              ; On            ;
; Ignore CARRY Buffers                                               ; Off             ; Off           ;
; Ignore CASCADE Buffers                                             ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off             ; Off           ;
; Ignore LCELL Buffers                                               ; Off             ; Off           ;
; Ignore SOFT Buffers                                                ; On              ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off             ; Off           ;
; Optimization Technique -- MAX II                                   ; Balanced        ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70              ; 70            ;
; Auto Carry Chains                                                  ; On              ; On            ;
; Auto Open-Drain Pins                                               ; On              ; On            ;
; Remove Duplicate Logic                                             ; On              ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off             ; Off           ;
; Perform gate-level register retiming                               ; Off             ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On              ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On              ; On            ;
; Auto RAM Block Balancing                                           ; On              ; On            ;
; Auto Resource Sharing                                              ; Off             ; Off           ;
; Enable M512                                                        ; On              ; On            ;
+--------------------------------------------------------------------+-----------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------+
; 2:1                ; 5 bits    ; 5 LEs         ; 5 LEs                ; 0 LEs                  ; Yes        ; |tiny16_MAXII|flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|wire_cntr5_q_int[0] ;
; 2:1                ; 8 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |tiny16_MAXII|flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|dffe8a[8]           ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |tiny16_MAXII|lcd_controller:lcd|count[3]                                                                         ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |tiny16_MAXII|tiny16:cpu|k[0]                                                                                     ;
; 5:1                ; 16 bits   ; 48 LEs        ; 32 LEs               ; 16 LEs                 ; Yes        ; |tiny16_MAXII|tiny16:cpu|pc[0]                                                                                    ;