📄 tiny16_maxii.vwf

📁 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核
💻 VWF
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	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("tiny16:cpu|k[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("tiny16:cpu|k[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 36454.986;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 181424.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 134096.0;
		}
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 62537.014;
	}
}

TRANSITION_LIST("tiny16:cpu|k[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 36454.986;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 181424.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 134096.0;
		}
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 62537.014;
	}
}

TRANSITION_LIST("tiny16:cpu|k[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4902.986;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 23664.0;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 181424.0;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 134096.0;
		}
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 62537.014;
	}
}

TRANSITION_LIST("tiny16:cpu|k[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 36454.986;
		NODE
		{
			REPEAT = 13;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 39440.0;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 15776.0;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 7888.0;
			LEVEL 1 FOR 7888.0;
			LEVEL 0 FOR 47328.0;
		}
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 39440.0;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 15776.0;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 7888.0;
		LEVEL 1 FOR 7888.0;
		LEVEL 0 FOR 23097.014;
	}
}

TRANSITION_LIST("tiny16:cpu|cflag")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 422966.986;
		LEVEL 1 FOR 15776.0;
		LEVEL 0 FOR 268192.0;
		LEVEL 1 FOR 15776.0;
		LEVEL 0 FOR 694144.0;
		LEVEL 1 FOR 15776.0;
		LEVEL 0 FOR 268192.0;
		LEVEL 1 FOR 15776.0;
		LEVEL 0 FOR 283401.014;
	}
}

TRANSITION_LIST("tiny16:cpu|zflag")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 138998.986;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 63104.0;
			LEVEL 0 FOR 78880.0;
		}
		NODE
		{
			REPEAT = 11;
			LEVEL 1 FOR 15776.0;
			LEVEL 0 FOR 126208.0;
		}
		LEVEL 1 FOR 15209.014;
	}
}

TRANSITION_LIST("flash:flash|fsm")
{
	NODE
	{
		REPEAT = 1;
		LEVEL fsm.idle FOR 414.986;
		LEVEL fsm.s1 FOR 4080.0;
		NODE
		{
			REPEAT = 252;
			LEVEL fsm.s2 FOR 136.0;
			LEVEL fsm.s3 FOR 136.0;
			LEVEL fsm.idle FOR 3672.0;
			LEVEL fsm.s1 FOR 3944.0;
		}
		LEVEL fsm.s2 FOR 136.0;
		LEVEL fsm.s3 FOR 136.0;
		LEVEL fsm.idle FOR 3672.0;
		LEVEL fsm.s1 FOR 3785.014;
	}
}

TRANSITION_LIST("temp_sdo")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 2000000.0;
	}
}

TRANSITION_LIST("temp_sck")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 186332.69;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 70992.0;
			LEVEL 0 FOR 70992.0;
		}
		LEVEL 1 FOR 70992.0;
		LEVEL 0 FOR 38867.31;
	}
}

TRANSITION_LIST("temp_ncs")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 91677.332;
		LEVEL 1 FOR 23664.0;
		LEVEL 0 FOR 1884658.668;
	}
}

TRANSITION_LIST("v_lcd_ena")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_e")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_rs")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_rw")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[7]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[6]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[5]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[4]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[3]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[2]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[1]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("lcd_db[0]~result")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_address[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_data[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL Z FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_ncs")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_noe")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("sram_nwe")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2000000.0;
	}
}

TRANSITION_LIST("tiny16:cpu|fsm")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 2000000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "led";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|ra[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|rx";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 18;
	TREE_LEVEL = 0;
	CHILDREN = 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|rx[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|rx[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "tiny16:cpu|rx[13]";
	EXPA
上一页 1 2 3 45
💿 文件大小 236 K
👤 上传用户 delsboy
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#ALtera #MAXII #PLD #IP核
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