tiny16_maxii.sim.rpt

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核

Simulator report for tiny16_MAXII
Thu Dec 02 11:15:56 2004
Version 4.2 Internal Build 142b 11/01/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. |tiny16_MAXII|flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|maxii_ufm:maxii_ufm_block1
  6. Simulator INI Usage
  7. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 2.0 ms       ;
; Simulation Netlist Size     ; 3040 nodes   ;
; Simulation Coverage         ;      42.80 % ;
; Total Number of Transitions ; 235307       ;
+-----------------------------+--------------+


+--------------------------------------------------------------------+
; Simulator Settings                                                 ;
+-------------------------------------------------------+------------+
; Option                                                ; Setting    ;
+-------------------------------------------------------+------------+
; Simulation mode                                       ; Functional ;
; Start time                                            ; 0ns        ;
; Add pins automatically to simulation output waveforms ; On         ;
; Check outputs                                         ; Off        ;
; Report simulation coverage                            ; On         ;
; Detect setup and hold time violations                 ; Off        ;
; Detect glitches                                       ; Off        ;
; Automatically save/load simulation netlist            ; Off        ;
; Disable timing delays in Timing Simulation            ; Off        ;
; Generate Signal Activity File                         ; Off        ;
+-------------------------------------------------------+------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------------------------------------------------------------+
; |tiny16_MAXII|flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|maxii_ufm:maxii_ufm_block1 ;
+--------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Beta Simulator
    Info: Version 4.2 Internal Build 142b 11/01/2004 SJ Full Version
    Info: Processing started: Thu Dec 02 11:15:47 2004
Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off tiny16_MAXII -c tiny16_MAXII
Warning: Wrong node type and/or width for node "|tiny16_MAXII|tiny16:cpu|fsm" in vector source file. Node in design is of type Enum and of width 1, but node in vector source file is of type 9-Level and of width 1.
Warning: Signal name "|tiny16_MAXII|tiny16:cpu|fsm" changed to enum type
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[7]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[6]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[5]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[4]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[3]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[2]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[1]"
Warning: Can't find signal in vector source file for input pin "|tiny16_MAXII|lcd_db[0]"
Info: System task: Info : UFM oscillator can operate at any frequency between 4.63MHz to 7.35Mhz.
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[7]"
    Info: Node "lcd_db[7]" has logic level of X
    Info: Node "lcd_controller:lcd|data~8" has logic level of 0
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[6]"
    Info: Node "lcd_db[6]" has logic level of X
    Info: Node "lcd_controller:lcd|data~9" has logic level of 0
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[5]"
    Info: Node "lcd_db[5]" has logic level of X
    Info: Node "lcd_controller:lcd|data~10" has logic level of 0
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[4]"
    Info: Node "lcd_db[4]" has logic level of X
    Info: Node "lcd_controller:lcd|data~11" has logic level of 0
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[3]"
    Info: Node "lcd_db[3]" has logic level of X
    Info: Node "lcd_controller:lcd|data~12" has logic level of 1
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[2]"
    Info: Node "lcd_db[2]" has logic level of X
    Info: Node "lcd_controller:lcd|data~13" has logic level of 1
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[1]"
    Info: Node "lcd_db[1]" has logic level of X
    Info: Node "lcd_controller:lcd|data~14" has logic level of 0
Warning: Found logic contention at time 116.01 us on bus node "|tiny16_MAXII|lcd_db[0]"
    Info: Node "lcd_db[0]" has logic level of X
    Info: Node "lcd_controller:lcd|data~15" has logic level of 0
Info: Simulation coverage is      42.80 %
Info: Number of transitions in simulation is 235307
Info: Quartus II Beta Simulator was successful. 0 errors, 18 warnings
    Info: Processing ended: Thu Dec 02 11:15:56 2004
    Info: Elapsed time: 00:00:10