lcd_controller.v

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核

module lcd_controller(
	clock,

	address,
	data_in,
	data_out,
	go_read,
	go_write,
	chipselect,
	complete,

	rs,
	rw,
	e,
	data);

parameter setup = 5;
parameter enable = 3;

parameter idle = 0;
parameter s1 = 1;
parameter s2 = 2;
parameter s3 = 3;
parameter s4 = 4;
parameter s5 = 5;

input			clock;

input			address;
input	[7:0]	data_in;
input			go_read;
input			go_write;
input			chipselect;

output	[7:0]	data_out;
output			complete;
output			rs;
output			rw;
output			e;

inout	[7:0]	data;

reg		[7:0]	data_out;
reg				complete;
reg				rs, rs_ena;
reg				rw, rw_ena;
reg				e, e_data, e_ena;
reg		[5:0]	fsm, next_state;
reg				count_ena, count_sclr;
reg		[3:0]	count;
reg				data_oe;

assign data = (data_oe == 1'b1) ? data_in : 8'bzzzz_zzzz;

always @ (posedge clock) begin
	fsm <= next_state;
	if(rs_ena == 1'b1)
		rs <= address & chipselect;
	if(rw_ena == 1'b1)
		rw <= go_read & chipselect;
	if(e_ena == 1'b1)
		e <= e_data;
	if(count_sclr == 1'b1)
		count <= 0;
	else
		if(count_ena == 1'b1)
			count <= count + 1;
	data_out <= data;
end

always @ (fsm, go_read, go_write, chipselect, count) begin
	e_ena <= 1'b0;
	count_sclr <= 1'b0;
	rs_ena <= 1'b0;
	rw_ena <= 1'b0;
	count_ena <= 1'b0;
	e_data <= 1'b0;
	data_oe <= 1'b0;
	complete <= 1'b0;
	next_state <= fsm;
	case(fsm)
		idle:begin
			rs_ena <= 1'b1;
			rw_ena <= 1'b1;
			e_ena <= 1'b1;
			count_sclr <= 1'b1;
			if((go_read & chipselect) == 1'b1) begin
				next_state <= s1;
			end
			if((go_write & chipselect) == 1'b1)
				next_state <= s3;
		end
		
		s1:begin
			count_ena <= 1'b1;
			e_data <= 1'b1;
			if(count == setup) begin
				count_sclr <= 1'b1;
				e_ena <= 1'b1;
				next_state <= s2;
			end
		end
		
		s2:begin
			count_ena <= 1'b1;
			if(count == enable) begin
				complete <= 1'b1;
				e_ena <= 1'b1;
				next_state <= idle;
			end
		end
		
		s3:begin
			count_ena <= 1'b1;
			e_data <= 1'b1;
			if(count == setup) begin
				count_sclr <= 1'b1;
				e_ena <= 1'b1;
				next_state <= s4;
			end
		end
		
		s4:begin
			count_ena <= 1'b1;
			data_oe <= 1'b1;
			if(count == enable) begin
				e_ena <= 1'b1;
				next_state <= s5;
			end
		end
		
		s5:begin
			complete <= 1'b1;
			next_state <= idle;
		end
	endcase
end

endmodule