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📁 这是8位微处理器的Verilog源代码

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        ldi     acc,#F0h        stm     acc,#20h        ; #20H = 0 (counter variable)        stacc   portall_over:        call    delay1_sec      ; delay for 1 sec        ldm     acc,#20h        ; get count value        oracci  #F0h            ; set LE high        stacc   port        andacci #EFh            ; set LE low        stacc   port        oracci  #F0h        stacc   port            ; set LE back high        ldm     acc,#20h                addacci #01h            ; increment count        stm     acc,#20h        cmpacci #10h        jne     check_input     ; if 10h, set to zero        ldi     acc,#F0h        stm     acc,#20hcheck_input:        ldacc   port            ; get port state into acc        andacci #80h            ; mask all but MSB        je      its_zero        ldi     acc,#F1h        stacc   port        ldi     acc,#D1h        stacc   port        ldi     acc,#F1h        jmp     all_overits_zero:        ldi     acc,#F0h        stacc   port        ldi     acc,#D0h        stacc   port        ldi     acc,#F0h        jmp     all_overdelay1_sec:        push    acc        ldi     acc,#ffhyy:     call    delay1_ms        subacci #01h        cmpacci #00h        jne     yy        pop     acc        retdelay1_ms:        push    acc        ldi     acc,#ffhxx:     subacci #01h        cmpacci #00h        cmpacci #00h        cmpacci #00h        jne     xx        pop     acc        ret        END

💿 文件大小 94 K

👤 上传用户 yangbaochun

📂 所属分类 VHDL/FPGA/Verilog

🏷️ 相关标签

#Verilog #8位微处理器 #源代码

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