inc.h

这是8位微处理器的Verilog源代码

//
// CLOCK DIVIDER
// 
// UNcomment the below to use a 
// clock divider.  This will allow a much
// faster external clock to be used and still
// slow down the internal core frequency.
// USE the paramter N in PC.V to adjust the
// frequency.  Minimum N is 3.
// COMMNET the below to use the external clock 
// directly as is.  Note that the core will 
// always run at 1/4 the external clock.
//
// `define use_clock_divider


//
//  DEBUG SIGNALS
//
//  UNcomment the below to activate the
//  test bus for observability during debug
//
// `define show_debug_pins