ledwater1.v

来自「用于测试ACEX1k30的流水灯程序」· Verilog 代码 · 共 21 行

module ledwater1(ledout,clk);
output[8:0] ledout;
input clk;
reg[8:0] ledout1;
reg[21:0] buffer;
initial
ledout1=9'b111111111;
always@(posedge clk)
begin
buffer=buffer+1;
if(buffer==22'b1111111111111111111111)
begin
ledout1=ledout1<<1;
if(ledout1==8'b00000000)
ledout1=9'b111111111;
end
end
assign ledout=ledout1;
endmodule