top.rpt

用于测试ACEX1k30的流水灯程序

-- Node name is '|ledwater1:1|:96' = '|ledwater1:1|buffer14' 
-- Equation name is '_LC3_D35', type is buried 
_LC3_D35 = DFFE( _EQ014, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ014 =  _LC3_D35 & !_LC4_D35
         # !_LC2_D34 &  _LC3_D35
         # !_LC2_D35 &  _LC3_D35
         #  _LC2_D34 &  _LC2_D35 & !_LC3_D35 &  _LC4_D35;

-- Node name is '|ledwater1:1|:95' = '|ledwater1:1|buffer15' 
-- Equation name is '_LC1_D35', type is buried 
_LC1_D35 = DFFE( _EQ015, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ015 =  _LC1_D35 & !_LC7_D35
         # !_LC1_D35 &  _LC7_D35;

-- Node name is '|ledwater1:1|:94' = '|ledwater1:1|buffer16' 
-- Equation name is '_LC2_D21', type is buried 
_LC2_D21 = DFFE( _EQ016, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ016 =  _LC2_D21 & !_LC5_D35
         # !_LC2_D21 &  _LC5_D35;

-- Node name is '|ledwater1:1|:93' = '|ledwater1:1|buffer17' 
-- Equation name is '_LC3_D29', type is buried 
_LC3_D29 = DFFE( _EQ017, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ017 = !_LC2_D21 &  _LC3_D29
         #  _LC3_D29 & !_LC5_D35
         #  _LC2_D21 & !_LC3_D29 &  _LC5_D35;

-- Node name is '|ledwater1:1|:92' = '|ledwater1:1|buffer18' 
-- Equation name is '_LC8_D29', type is buried 
_LC8_D29 = DFFE( _EQ018, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ018 = !_LC2_D21 &  _LC8_D29
         # !_LC5_D35 &  _LC8_D29
         # !_LC3_D29 &  _LC8_D29
         #  _LC2_D21 &  _LC3_D29 &  _LC5_D35 & !_LC8_D29;

-- Node name is '|ledwater1:1|:91' = '|ledwater1:1|buffer19' 
-- Equation name is '_LC7_D29', type is buried 
_LC7_D29 = DFFE( _EQ019, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ019 = !_LC4_D29 &  _LC7_D29
         #  _LC4_D29 & !_LC7_D29;

-- Node name is '|ledwater1:1|:90' = '|ledwater1:1|buffer20' 
-- Equation name is '_LC5_D29', type is buried 
_LC5_D29 = DFFE( _EQ020, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ020 =  _LC5_D29 & !_LC7_D29
         # !_LC4_D29 &  _LC5_D29
         #  _LC4_D29 & !_LC5_D29 &  _LC7_D29;

-- Node name is '|ledwater1:1|:89' = '|ledwater1:1|buffer21' 
-- Equation name is '_LC6_D29', type is buried 
_LC6_D29 = DFFE( _EQ021, GLOBAL( GCLK),  VCC,  VCC,  VCC);
  _EQ021 =  _LC6_D29 & !_LC7_D29
         # !_LC4_D29 &  _LC6_D29
         # !_LC5_D29 &  _LC6_D29
         #  _LC4_D29 &  _LC5_D29 & !_LC6_D29 &  _LC7_D29;

-- Node name is '|ledwater1:1|:167' = '|ledwater1:1|ledout10' 
-- Equation name is '_LC5_C30', type is buried 
_LC5_C30 = DFFE( _EQ022, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ022 = !_LC5_C30 &  _LC8_C30;

-- Node name is '|ledwater1:1|:166' = '|ledwater1:1|ledout11' 
-- Equation name is '_LC7_C30', type is buried 
_LC7_C30 = DFFE( _EQ023, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ023 =  _LC8_C30
         #  _LC5_C30;

-- Node name is '|ledwater1:1|:165' = '|ledwater1:1|ledout12' 
-- Equation name is '_LC2_C30', type is buried 
_LC2_C30 = DFFE( _EQ024, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ024 = !_LC5_C30 &  _LC8_C30
         #  _LC7_C30;

-- Node name is '|ledwater1:1|:164' = '|ledwater1:1|ledout13' 
-- Equation name is '_LC6_C30', type is buried 
_LC6_C30 = DFFE( _EQ025, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ025 = !_LC5_C30 &  _LC8_C30
         #  _LC2_C30;

-- Node name is '|ledwater1:1|:163' = '|ledwater1:1|ledout14' 
-- Equation name is '_LC4_C30', type is buried 
_LC4_C30 = DFFE( _EQ026, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ026 = !_LC5_C30 &  _LC8_C30
         #  _LC6_C30;

-- Node name is '|ledwater1:1|:162' = '|ledwater1:1|ledout15' 
-- Equation name is '_LC1_C30', type is buried 
_LC1_C30 = DFFE( _EQ027, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ027 = !_LC5_C30 &  _LC8_C30
         #  _LC4_C30;

-- Node name is '|ledwater1:1|:161' = '|ledwater1:1|ledout16' 
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = DFFE( _EQ028, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ028 = !_LC5_C30 &  _LC8_C30
         #  _LC1_C30;

-- Node name is '|ledwater1:1|:160' = '|ledwater1:1|ledout17' 
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = DFFE( _EQ029, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ029 = !_LC5_C30 &  _LC8_C30
         #  _LC2_C20;

-- Node name is '|ledwater1:1|:159' = '|ledwater1:1|ledout18' 
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = DFFE( _EQ030, GLOBAL( GCLK),  VCC,  VCC,  _LC7_D33);
  _EQ030 = !_LC5_C30 &  _LC8_C30
         #  _LC3_C20;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D33', type is buried 
_LC2_D33 = LCELL( _EQ031);
  _EQ031 =  _LC1_D33 &  _LC3_D33 &  _LC5_D33;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_D26', type is buried 
_LC4_D26 = LCELL( _EQ032);
  _EQ032 =  _LC2_D33 &  _LC3_D26 &  _LC4_D33 &  _LC6_D26;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D26', type is buried 
_LC2_D26 = LCELL( _EQ033);
  _EQ033 =  _LC4_D26 &  _LC5_D26 &  _LC7_D26 &  _LC8_D26;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_D34', type is buried 
_LC2_D34 = LCELL( _EQ034);
  _EQ034 =  _LC1_D34 &  _LC2_D26 &  _LC3_D34 &  _LC5_D34;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_D35', type is buried 
_LC7_D35 = LCELL( _EQ035);
  _EQ035 =  _LC2_D34 &  _LC2_D35 &  _LC3_D35 &  _LC4_D35;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D35', type is buried 
_LC5_D35 = LCELL( _EQ036);
  _EQ036 =  _LC1_D35 &  _LC7_D35;

-- Node name is '|ledwater1:1|lpm_add_sub:186|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_D29', type is buried 
_LC4_D29 = LCELL( _EQ037);
  _EQ037 =  _LC2_D21 &  _LC3_D29 &  _LC5_D35 &  _LC8_D29;

-- Node name is '|ledwater1:1|~20~1' 
-- Equation name is '_LC3_C30', type is buried 
-- synthesized logic cell 
_LC3_C30 = LCELL( _EQ038);
  _EQ038 = !_LC2_C30 & !_LC4_C30 & !_LC6_C30 & !_LC7_C30;

-- Node name is '|ledwater1:1|~20~2' 
-- Equation name is '_LC8_C30', type is buried 
-- synthesized logic cell 
_LC8_C30 = LCELL( _EQ039);
  _EQ039 = !_LC1_C30 & !_LC2_C20 & !_LC3_C20 &  _LC3_C30;

-- Node name is '|ledwater1:1|~133~1' 
-- Equation name is '_LC6_D35', type is buried 
-- synthesized logic cell 
_LC6_D35 = LCELL( _EQ040);
  _EQ040 =  _LC2_D35 &  _LC3_D34 &  _LC4_D35 &  _LC5_D34;

-- Node name is '|ledwater1:1|~133~2' 
-- Equation name is '_LC2_D29', type is buried 
-- synthesized logic cell 
_LC2_D29 = LCELL( _EQ041);
  _EQ041 =  _LC1_D35 &  _LC2_D21 &  _LC3_D29 &  _LC3_D35;

-- Node name is '|ledwater1:1|~133~3' 
-- Equation name is '_LC1_D29', type is buried 
-- synthesized logic cell 
_LC1_D29 = LCELL( _EQ042);
  _EQ042 =  _LC5_D29 &  _LC6_D29 &  _LC7_D29 &  _LC8_D29;

-- Node name is '|ledwater1:1|~133~4' 
-- Equation name is '_LC6_D33', type is buried 
-- synthesized logic cell 
_LC6_D33 = LCELL( _EQ043);
  _EQ043 =  _LC1_D33 &  _LC3_D26 &  _LC4_D33 &  _LC6_D26;

-- Node name is '|ledwater1:1|~133~5' 
-- Equation name is '_LC1_D26', type is buried 
-- synthesized logic cell 
_LC1_D26 = LCELL( _EQ044);
  _EQ044 =  _LC1_D34 &  _LC5_D26 &  _LC7_D26 &  _LC8_D26;

-- Node name is '|ledwater1:1|~133~6' 
-- Equation name is '_LC8_D33', type is buried 
-- synthesized logic cell 
_LC8_D33 = LCELL( _EQ045);
  _EQ045 =  _LC1_D26 &  _LC3_D33 & !_LC5_D33 &  _LC6_D33;

-- Node name is '|ledwater1:1|:133' 
-- Equation name is '_LC7_D33', type is buried 
_LC7_D33 = LCELL( _EQ046);
  _EQ046 =  _LC1_D29 &  _LC2_D29 &  _LC6_D35 &  _LC8_D33;



Project Information           d:\project\microseim\acex1k\1026\ledtest\top.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,327K