📄 top.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\microseim\acex1k\1026\ledtest\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - D 33 AND2 0 3 0 3 |ledwater1:1|lpm_add_sub:186|addcore:adder|:131
- 4 - D 26 AND2 0 4 0 4 |ledwater1:1|lpm_add_sub:186|addcore:adder|:143
- 2 - D 26 AND2 0 4 0 4 |ledwater1:1|lpm_add_sub:186|addcore:adder|:155
- 2 - D 34 AND2 0 4 0 4 |ledwater1:1|lpm_add_sub:186|addcore:adder|:167
- 7 - D 35 AND2 0 4 0 2 |ledwater1:1|lpm_add_sub:186|addcore:adder|:179
- 5 - D 35 AND2 0 2 0 4 |ledwater1:1|lpm_add_sub:186|addcore:adder|:183
- 4 - D 29 AND2 0 4 0 3 |ledwater1:1|lpm_add_sub:186|addcore:adder|:195
- 3 - C 30 AND2 s 0 4 0 1 |ledwater1:1|~20~1
- 8 - C 30 AND2 s 0 4 0 9 |ledwater1:1|~20~2
- 6 - D 29 DFFE + 0 3 0 1 |ledwater1:1|buffer21 (|ledwater1:1|:89)
- 5 - D 29 DFFE + 0 2 0 2 |ledwater1:1|buffer20 (|ledwater1:1|:90)
- 7 - D 29 DFFE + 0 1 0 3 |ledwater1:1|buffer19 (|ledwater1:1|:91)
- 8 - D 29 DFFE + 0 3 0 2 |ledwater1:1|buffer18 (|ledwater1:1|:92)
- 3 - D 29 DFFE + 0 2 0 3 |ledwater1:1|buffer17 (|ledwater1:1|:93)
- 2 - D 21 DFFE + 0 1 0 4 |ledwater1:1|buffer16 (|ledwater1:1|:94)
- 1 - D 35 DFFE + 0 1 0 2 |ledwater1:1|buffer15 (|ledwater1:1|:95)
- 3 - D 35 DFFE + 0 3 0 2 |ledwater1:1|buffer14 (|ledwater1:1|:96)
- 2 - D 35 DFFE + 0 2 0 3 |ledwater1:1|buffer13 (|ledwater1:1|:97)
- 4 - D 35 DFFE + 0 1 0 4 |ledwater1:1|buffer12 (|ledwater1:1|:98)
- 3 - D 34 DFFE + 0 3 0 2 |ledwater1:1|buffer11 (|ledwater1:1|:99)
- 5 - D 34 DFFE + 0 2 0 3 |ledwater1:1|buffer10 (|ledwater1:1|:100)
- 1 - D 34 DFFE + 0 1 0 4 |ledwater1:1|buffer9 (|ledwater1:1|:101)
- 5 - D 26 DFFE + 0 3 0 2 |ledwater1:1|buffer8 (|ledwater1:1|:102)
- 7 - D 26 DFFE + 0 2 0 3 |ledwater1:1|buffer7 (|ledwater1:1|:103)
- 8 - D 26 DFFE + 0 1 0 4 |ledwater1:1|buffer6 (|ledwater1:1|:104)
- 3 - D 26 DFFE + 0 3 0 2 |ledwater1:1|buffer5 (|ledwater1:1|:105)
- 6 - D 26 DFFE + 0 2 0 3 |ledwater1:1|buffer4 (|ledwater1:1|:106)
- 4 - D 33 DFFE + 0 3 0 4 |ledwater1:1|buffer3 (|ledwater1:1|:107)
- 1 - D 33 DFFE + 0 2 0 3 |ledwater1:1|buffer2 (|ledwater1:1|:108)
- 3 - D 33 DFFE + 0 1 0 4 |ledwater1:1|buffer1 (|ledwater1:1|:109)
- 5 - D 33 DFFE + 0 0 0 5 |ledwater1:1|buffer0 (|ledwater1:1|:110)
- 6 - D 35 AND2 s 0 4 0 1 |ledwater1:1|~133~1
- 2 - D 29 AND2 s 0 4 0 1 |ledwater1:1|~133~2
- 1 - D 29 AND2 s 0 4 0 1 |ledwater1:1|~133~3
- 6 - D 33 AND2 s 0 4 0 1 |ledwater1:1|~133~4
- 1 - D 26 AND2 s 0 4 0 1 |ledwater1:1|~133~5
- 8 - D 33 AND2 s 0 4 0 1 |ledwater1:1|~133~6
- 7 - D 33 AND2 0 4 0 9 |ledwater1:1|:133
- 5 - C 20 DFFE + 0 4 1 0 |ledwater1:1|ledout18 (|ledwater1:1|:159)
- 3 - C 20 DFFE + 0 4 1 2 |ledwater1:1|ledout17 (|ledwater1:1|:160)
- 2 - C 20 DFFE + 0 4 1 2 |ledwater1:1|ledout16 (|ledwater1:1|:161)
- 1 - C 30 DFFE + 0 4 1 2 |ledwater1:1|ledout15 (|ledwater1:1|:162)
- 4 - C 30 DFFE + 0 4 1 2 |ledwater1:1|ledout14 (|ledwater1:1|:163)
- 6 - C 30 DFFE + 0 4 1 2 |ledwater1:1|ledout13 (|ledwater1:1|:164)
- 2 - C 30 DFFE + 0 4 1 2 |ledwater1:1|ledout12 (|ledwater1:1|:165)
- 7 - C 30 DFFE + 0 3 1 2 |ledwater1:1|ledout11 (|ledwater1:1|:166)
- 5 - C 30 DFFE + 0 2 1 8 |ledwater1:1|ledout10 (|ledwater1:1|:167)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\project\microseim\acex1k\1026\ledtest\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 3/144( 2%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
D: 18/144( 12%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\microseim\acex1k\1026\ledtest\top.rpt
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** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 GCLK
Device-Specific Information: d:\project\microseim\acex1k\1026\ledtest\top.rpt
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** EQUATIONS **
GCLK : INPUT;
-- Node name is 'LEDOUT0'
-- Equation name is 'LEDOUT0', type is output
LEDOUT0 = _LC5_C30;
-- Node name is 'LEDOUT1'
-- Equation name is 'LEDOUT1', type is output
LEDOUT1 = _LC7_C30;
-- Node name is 'LEDOUT2'
-- Equation name is 'LEDOUT2', type is output
LEDOUT2 = _LC2_C30;
-- Node name is 'LEDOUT3'
-- Equation name is 'LEDOUT3', type is output
LEDOUT3 = _LC6_C30;
-- Node name is 'LEDOUT4'
-- Equation name is 'LEDOUT4', type is output
LEDOUT4 = _LC4_C30;
-- Node name is 'LEDOUT5'
-- Equation name is 'LEDOUT5', type is output
LEDOUT5 = _LC1_C30;
-- Node name is 'LEDOUT6'
-- Equation name is 'LEDOUT6', type is output
LEDOUT6 = _LC2_C20;
-- Node name is 'LEDOUT7'
-- Equation name is 'LEDOUT7', type is output
LEDOUT7 = _LC3_C20;
-- Node name is 'LEDOUT8'
-- Equation name is 'LEDOUT8', type is output
LEDOUT8 = _LC5_C20;
-- Node name is '|ledwater1:1|:110' = '|ledwater1:1|buffer0'
-- Equation name is '_LC5_D33', type is buried
_LC5_D33 = DFFE(!_LC5_D33, GLOBAL( GCLK), VCC, VCC, VCC);
-- Node name is '|ledwater1:1|:109' = '|ledwater1:1|buffer1'
-- Equation name is '_LC3_D33', type is buried
_LC3_D33 = DFFE( _EQ001, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ001 = !_LC3_D33 & _LC5_D33
# _LC3_D33 & !_LC5_D33;
-- Node name is '|ledwater1:1|:108' = '|ledwater1:1|buffer2'
-- Equation name is '_LC1_D33', type is buried
_LC1_D33 = DFFE( _EQ002, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ002 = _LC1_D33 & !_LC5_D33
# _LC1_D33 & !_LC3_D33
# !_LC1_D33 & _LC3_D33 & _LC5_D33;
-- Node name is '|ledwater1:1|:107' = '|ledwater1:1|buffer3'
-- Equation name is '_LC4_D33', type is buried
_LC4_D33 = DFFE( _EQ003, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ003 = !_LC1_D33 & _LC4_D33
# _LC4_D33 & !_LC5_D33
# !_LC3_D33 & _LC4_D33
# _LC1_D33 & _LC3_D33 & !_LC4_D33 & _LC5_D33;
-- Node name is '|ledwater1:1|:106' = '|ledwater1:1|buffer4'
-- Equation name is '_LC6_D26', type is buried
_LC6_D26 = DFFE( _EQ004, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ004 = !_LC4_D33 & _LC6_D26
# !_LC2_D33 & _LC6_D26
# _LC2_D33 & _LC4_D33 & !_LC6_D26;
-- Node name is '|ledwater1:1|:105' = '|ledwater1:1|buffer5'
-- Equation name is '_LC3_D26', type is buried
_LC3_D26 = DFFE( _EQ005, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ005 = _LC3_D26 & !_LC4_D33
# !_LC2_D33 & _LC3_D26
# _LC3_D26 & !_LC6_D26
# _LC2_D33 & !_LC3_D26 & _LC4_D33 & _LC6_D26;
-- Node name is '|ledwater1:1|:104' = '|ledwater1:1|buffer6'
-- Equation name is '_LC8_D26', type is buried
_LC8_D26 = DFFE( _EQ006, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ006 = !_LC4_D26 & _LC8_D26
# _LC4_D26 & !_LC8_D26;
-- Node name is '|ledwater1:1|:103' = '|ledwater1:1|buffer7'
-- Equation name is '_LC7_D26', type is buried
_LC7_D26 = DFFE( _EQ007, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ007 = _LC7_D26 & !_LC8_D26
# !_LC4_D26 & _LC7_D26
# _LC4_D26 & !_LC7_D26 & _LC8_D26;
-- Node name is '|ledwater1:1|:102' = '|ledwater1:1|buffer8'
-- Equation name is '_LC5_D26', type is buried
_LC5_D26 = DFFE( _EQ008, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ008 = _LC5_D26 & !_LC7_D26
# _LC5_D26 & !_LC8_D26
# !_LC4_D26 & _LC5_D26
# _LC4_D26 & !_LC5_D26 & _LC7_D26 & _LC8_D26;
-- Node name is '|ledwater1:1|:101' = '|ledwater1:1|buffer9'
-- Equation name is '_LC1_D34', type is buried
_LC1_D34 = DFFE( _EQ009, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ009 = _LC1_D34 & !_LC2_D26
# !_LC1_D34 & _LC2_D26;
-- Node name is '|ledwater1:1|:100' = '|ledwater1:1|buffer10'
-- Equation name is '_LC5_D34', type is buried
_LC5_D34 = DFFE( _EQ010, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ010 = !_LC1_D34 & _LC5_D34
# !_LC2_D26 & _LC5_D34
# _LC1_D34 & _LC2_D26 & !_LC5_D34;
-- Node name is '|ledwater1:1|:99' = '|ledwater1:1|buffer11'
-- Equation name is '_LC3_D34', type is buried
_LC3_D34 = DFFE( _EQ011, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ011 = _LC3_D34 & !_LC5_D34
# !_LC1_D34 & _LC3_D34
# !_LC2_D26 & _LC3_D34
# _LC1_D34 & _LC2_D26 & !_LC3_D34 & _LC5_D34;
-- Node name is '|ledwater1:1|:98' = '|ledwater1:1|buffer12'
-- Equation name is '_LC4_D35', type is buried
_LC4_D35 = DFFE( _EQ012, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ012 = !_LC2_D34 & _LC4_D35
# _LC2_D34 & !_LC4_D35;
-- Node name is '|ledwater1:1|:97' = '|ledwater1:1|buffer13'
-- Equation name is '_LC2_D35', type is buried
_LC2_D35 = DFFE( _EQ013, GLOBAL( GCLK), VCC, VCC, VCC);
_EQ013 = _LC2_D35 & !_LC4_D35
# !_LC2_D34 & _LC2_D35
# _LC2_D34 & !_LC2_D35 & _LC4_D35;
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