ledwater1.rpt

用于测试ACEX1k30的流水灯程序

  _EQ019 =  buffer19 & !_LC3_C23
         # !buffer19 &  _LC3_C23;

-- Node name is ':90' = 'buffer20' 
-- Equation name is 'buffer20', location is LC4_C23, type is buried.
buffer20 = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 = !buffer19 &  buffer20
         #  buffer20 & !_LC3_C23
         #  buffer19 & !buffer20 &  _LC3_C23;

-- Node name is ':89' = 'buffer21' 
-- Equation name is 'buffer21', location is LC6_C23, type is buried.
buffer21 = DFFE( _EQ021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ021 = !buffer19 &  buffer21
         #  buffer21 & !_LC3_C23
         # !buffer20 &  buffer21
         #  buffer19 &  buffer20 & !buffer21 &  _LC3_C23;

-- Node name is 'ledout0' 
-- Equation name is 'ledout0', type is output 
ledout0  =  ledout10;

-- Node name is 'ledout1' 
-- Equation name is 'ledout1', type is output 
ledout1  =  ledout11;

-- Node name is 'ledout2' 
-- Equation name is 'ledout2', type is output 
ledout2  =  ledout12;

-- Node name is 'ledout3' 
-- Equation name is 'ledout3', type is output 
ledout3  =  ledout13;

-- Node name is 'ledout4' 
-- Equation name is 'ledout4', type is output 
ledout4  =  ledout14;

-- Node name is 'ledout5' 
-- Equation name is 'ledout5', type is output 
ledout5  =  ledout15;

-- Node name is 'ledout6' 
-- Equation name is 'ledout6', type is output 
ledout6  =  ledout16;

-- Node name is 'ledout7' 
-- Equation name is 'ledout7', type is output 
ledout7  =  ledout17;

-- Node name is 'ledout8' 
-- Equation name is 'ledout8', type is output 
ledout8  =  ledout18;

-- Node name is ':167' = 'ledout10' 
-- Equation name is 'ledout10', location is LC5_C31, type is buried.
ledout10 = DFFE( _EQ022, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ022 =  _LC1_C28 & !ledout10;

-- Node name is ':166' = 'ledout11' 
-- Equation name is 'ledout11', location is LC7_C31, type is buried.
ledout11 = DFFE( _EQ023, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ023 =  _LC1_C28
         #  ledout10;

-- Node name is ':165' = 'ledout12' 
-- Equation name is 'ledout12', location is LC3_C31, type is buried.
ledout12 = DFFE( _EQ024, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ024 =  _LC1_C28 & !ledout10
         #  ledout11;

-- Node name is ':164' = 'ledout13' 
-- Equation name is 'ledout13', location is LC6_C31, type is buried.
ledout13 = DFFE( _EQ025, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ025 =  _LC1_C28 & !ledout10
         #  ledout12;

-- Node name is ':163' = 'ledout14' 
-- Equation name is 'ledout14', location is LC1_C31, type is buried.
ledout14 = DFFE( _EQ026, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ026 =  _LC1_C28 & !ledout10
         #  ledout13;

-- Node name is ':162' = 'ledout15' 
-- Equation name is 'ledout15', location is LC2_C31, type is buried.
ledout15 = DFFE( _EQ027, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ027 =  _LC1_C28 & !ledout10
         #  ledout14;

-- Node name is ':161' = 'ledout16' 
-- Equation name is 'ledout16', location is LC2_C28, type is buried.
ledout16 = DFFE( _EQ028, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ028 =  _LC1_C28 & !ledout10
         #  ledout15;

-- Node name is ':160' = 'ledout17' 
-- Equation name is 'ledout17', location is LC4_C28, type is buried.
ledout17 = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ029 =  _LC1_C28 & !ledout10
         #  ledout16;

-- Node name is ':159' = 'ledout18' 
-- Equation name is 'ledout18', location is LC4_C31, type is buried.
ledout18 = DFFE( _EQ030, GLOBAL( clk),  VCC,  VCC,  _LC1_C36);
  _EQ030 =  _LC1_C28 & !ledout10
         #  ledout17;

-- Node name is '|lpm_add_sub:186|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C36', type is buried 
_LC2_C36 = LCELL( _EQ031);
  _EQ031 =  buffer0 &  buffer1 &  buffer2;

-- Node name is '|lpm_add_sub:186|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C27', type is buried 
_LC4_C27 = LCELL( _EQ032);
  _EQ032 =  buffer3 &  buffer4 &  buffer5 &  _LC2_C36;

-- Node name is '|lpm_add_sub:186|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C27', type is buried 
_LC2_C27 = LCELL( _EQ033);
  _EQ033 =  buffer6 &  buffer7 &  buffer8 &  _LC4_C27;

-- Node name is '|lpm_add_sub:186|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C26', type is buried 
_LC2_C26 = LCELL( _EQ034);
  _EQ034 =  buffer9 &  buffer10 &  buffer11 &  _LC2_C27;

-- Node name is '|lpm_add_sub:186|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C24', type is buried 
_LC6_C24 = LCELL( _EQ035);
  _EQ035 =  buffer12 &  buffer13 &  buffer14 &  _LC2_C26;

-- Node name is '|lpm_add_sub:186|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C24', type is buried 
_LC3_C24 = LCELL( _EQ036);
  _EQ036 =  buffer15 &  _LC6_C24;

-- Node name is '|lpm_add_sub:186|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ037);
  _EQ037 =  buffer16 &  buffer17 &  buffer18 &  _LC3_C24;

-- Node name is '~20~1' 
-- Equation name is '~20~1', location is LC8_C31, type is buried.
-- synthesized logic cell 
_LC8_C31 = LCELL( _EQ038);
  _EQ038 = !ledout11 & !ledout12 & !ledout13 & !ledout14;

-- Node name is '~20~2' 
-- Equation name is '~20~2', location is LC1_C28, type is buried.
-- synthesized logic cell 
_LC1_C28 = LCELL( _EQ039);
  _EQ039 =  _LC8_C31 & !ledout15 & !ledout16 & !ledout17;

-- Node name is '~133~1' 
-- Equation name is '~133~1', location is LC8_C24, type is buried.
-- synthesized logic cell 
_LC8_C24 = LCELL( _EQ040);
  _EQ040 =  buffer10 &  buffer11 &  buffer12 &  buffer13;

-- Node name is '~133~2' 
-- Equation name is '~133~2', location is LC2_C23, type is buried.
-- synthesized logic cell 
_LC2_C23 = LCELL( _EQ041);
  _EQ041 =  buffer14 &  buffer15 &  buffer16 &  buffer17;

-- Node name is '~133~3' 
-- Equation name is '~133~3', location is LC5_C23, type is buried.
-- synthesized logic cell 
_LC5_C23 = LCELL( _EQ042);
  _EQ042 =  buffer18 &  buffer19 &  buffer20 &  buffer21;

-- Node name is '~133~4' 
-- Equation name is '~133~4', location is LC5_C27, type is buried.
-- synthesized logic cell 
_LC5_C27 = LCELL( _EQ043);
  _EQ043 =  buffer2 &  buffer3 &  buffer4 &  buffer5;

-- Node name is '~133~5' 
-- Equation name is '~133~5', location is LC1_C27, type is buried.
-- synthesized logic cell 
_LC1_C27 = LCELL( _EQ044);
  _EQ044 =  buffer6 &  buffer7 &  buffer8 &  buffer9;

-- Node name is '~133~6' 
-- Equation name is '~133~6', location is LC7_C36, type is buried.
-- synthesized logic cell 
_LC7_C36 = LCELL( _EQ045);
  _EQ045 = !buffer0 &  buffer1 &  _LC1_C27 &  _LC5_C27;

-- Node name is ':133' 
-- Equation name is '_LC1_C36', type is buried 
_LC1_C36 = LCELL( _EQ046);
  _EQ046 =  _LC2_C23 &  _LC5_C23 &  _LC7_C36 &  _LC8_C24;



Project Information     d:\project\microseim\acex1k\1026\ledtest\ledwater1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,932K