📄 ledwater1.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\project\microseim\acex1k\1026\ledtest\ledwater1.rpt
ledwater1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 36 AND2 0 3 0 3 |lpm_add_sub:186|addcore:adder|:131
- 4 - C 27 AND2 0 4 0 4 |lpm_add_sub:186|addcore:adder|:143
- 2 - C 27 AND2 0 4 0 4 |lpm_add_sub:186|addcore:adder|:155
- 2 - C 26 AND2 0 4 0 4 |lpm_add_sub:186|addcore:adder|:167
- 6 - C 24 AND2 0 4 0 2 |lpm_add_sub:186|addcore:adder|:179
- 3 - C 24 AND2 0 2 0 4 |lpm_add_sub:186|addcore:adder|:183
- 3 - C 23 AND2 0 4 0 3 |lpm_add_sub:186|addcore:adder|:195
- 8 - C 31 AND2 s 0 4 0 1 ~20~1
- 1 - C 28 AND2 s 0 4 0 9 ~20~2
- 6 - C 23 DFFE + 0 3 0 1 buffer21 (:89)
- 4 - C 23 DFFE + 0 2 0 2 buffer20 (:90)
- 7 - C 23 DFFE + 0 1 0 3 buffer19 (:91)
- 8 - C 23 DFFE + 0 3 0 2 buffer18 (:92)
- 1 - C 23 DFFE + 0 2 0 3 buffer17 (:93)
- 2 - C 29 DFFE + 0 1 0 4 buffer16 (:94)
- 1 - C 24 DFFE + 0 1 0 2 buffer15 (:95)
- 4 - C 24 DFFE + 0 3 0 2 buffer14 (:96)
- 2 - C 24 DFFE + 0 2 0 3 buffer13 (:97)
- 5 - C 24 DFFE + 0 1 0 4 buffer12 (:98)
- 1 - C 26 DFFE + 0 3 0 2 buffer11 (:99)
- 6 - C 26 DFFE + 0 2 0 3 buffer10 (:100)
- 5 - C 26 DFFE + 0 1 0 4 buffer9 (:101)
- 6 - C 27 DFFE + 0 3 0 2 buffer8 (:102)
- 7 - C 27 DFFE + 0 2 0 3 buffer7 (:103)
- 8 - C 27 DFFE + 0 1 0 4 buffer6 (:104)
- 3 - C 27 DFFE + 0 3 0 2 buffer5 (:105)
- 4 - C 36 DFFE + 0 2 0 3 buffer4 (:106)
- 8 - C 36 DFFE + 0 3 0 4 buffer3 (:107)
- 5 - C 36 DFFE + 0 2 0 3 buffer2 (:108)
- 3 - C 36 DFFE + 0 1 0 4 buffer1 (:109)
- 6 - C 36 DFFE + 0 0 0 5 buffer0 (:110)
- 8 - C 24 AND2 s 0 4 0 1 ~133~1
- 2 - C 23 AND2 s 0 4 0 1 ~133~2
- 5 - C 23 AND2 s 0 4 0 1 ~133~3
- 5 - C 27 AND2 s 0 4 0 1 ~133~4
- 1 - C 27 AND2 s 0 4 0 1 ~133~5
- 7 - C 36 AND2 s 0 4 0 1 ~133~6
- 1 - C 36 AND2 0 4 0 9 :133
- 4 - C 31 DFFE + 0 4 1 0 ledout18 (:159)
- 4 - C 28 DFFE + 0 4 1 2 ledout17 (:160)
- 2 - C 28 DFFE + 0 4 1 2 ledout16 (:161)
- 2 - C 31 DFFE + 0 4 1 2 ledout15 (:162)
- 1 - C 31 DFFE + 0 4 1 2 ledout14 (:163)
- 6 - C 31 DFFE + 0 4 1 2 ledout13 (:164)
- 3 - C 31 DFFE + 0 4 1 2 ledout12 (:165)
- 7 - C 31 DFFE + 0 3 1 2 ledout11 (:166)
- 5 - C 31 DFFE + 0 2 1 8 ledout10 (:167)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information:d:\project\microseim\acex1k\1026\ledtest\ledwater1.rpt
ledwater1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 23/144( 15%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\project\microseim\acex1k\1026\ledtest\ledwater1.rpt
ledwater1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 clk
Device-Specific Information:d:\project\microseim\acex1k\1026\ledtest\ledwater1.rpt
ledwater1
** EQUATIONS **
clk : INPUT;
-- Node name is ':110' = 'buffer0'
-- Equation name is 'buffer0', location is LC6_C36, type is buried.
buffer0 = DFFE(!buffer0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':109' = 'buffer1'
-- Equation name is 'buffer1', location is LC3_C36, type is buried.
buffer1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = buffer0 & !buffer1
# !buffer0 & buffer1;
-- Node name is ':108' = 'buffer2'
-- Equation name is 'buffer2', location is LC5_C36, type is buried.
buffer2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !buffer0 & buffer2
# !buffer1 & buffer2
# buffer0 & buffer1 & !buffer2;
-- Node name is ':107' = 'buffer3'
-- Equation name is 'buffer3', location is LC8_C36, type is buried.
buffer3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !buffer2 & buffer3
# !buffer0 & buffer3
# !buffer1 & buffer3
# buffer0 & buffer1 & buffer2 & !buffer3;
-- Node name is ':106' = 'buffer4'
-- Equation name is 'buffer4', location is LC4_C36, type is buried.
buffer4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !buffer3 & buffer4
# buffer4 & !_LC2_C36
# buffer3 & !buffer4 & _LC2_C36;
-- Node name is ':105' = 'buffer5'
-- Equation name is 'buffer5', location is LC3_C27, type is buried.
buffer5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !buffer3 & buffer5
# buffer5 & !_LC2_C36
# !buffer4 & buffer5
# buffer3 & buffer4 & !buffer5 & _LC2_C36;
-- Node name is ':104' = 'buffer6'
-- Equation name is 'buffer6', location is LC8_C27, type is buried.
buffer6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = buffer6 & !_LC4_C27
# !buffer6 & _LC4_C27;
-- Node name is ':103' = 'buffer7'
-- Equation name is 'buffer7', location is LC7_C27, type is buried.
buffer7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !buffer6 & buffer7
# buffer7 & !_LC4_C27
# buffer6 & !buffer7 & _LC4_C27;
-- Node name is ':102' = 'buffer8'
-- Equation name is 'buffer8', location is LC6_C27, type is buried.
buffer8 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !buffer7 & buffer8
# !buffer6 & buffer8
# buffer8 & !_LC4_C27
# buffer6 & buffer7 & !buffer8 & _LC4_C27;
-- Node name is ':101' = 'buffer9'
-- Equation name is 'buffer9', location is LC5_C26, type is buried.
buffer9 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = buffer9 & !_LC2_C27
# !buffer9 & _LC2_C27;
-- Node name is ':100' = 'buffer10'
-- Equation name is 'buffer10', location is LC6_C26, type is buried.
buffer10 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !buffer9 & buffer10
# buffer10 & !_LC2_C27
# buffer9 & !buffer10 & _LC2_C27;
-- Node name is ':99' = 'buffer11'
-- Equation name is 'buffer11', location is LC1_C26, type is buried.
buffer11 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !buffer10 & buffer11
# !buffer9 & buffer11
# buffer11 & !_LC2_C27
# buffer9 & buffer10 & !buffer11 & _LC2_C27;
-- Node name is ':98' = 'buffer12'
-- Equation name is 'buffer12', location is LC5_C24, type is buried.
buffer12 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = buffer12 & !_LC2_C26
# !buffer12 & _LC2_C26;
-- Node name is ':97' = 'buffer13'
-- Equation name is 'buffer13', location is LC2_C24, type is buried.
buffer13 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !buffer12 & buffer13
# buffer13 & !_LC2_C26
# buffer12 & !buffer13 & _LC2_C26;
-- Node name is ':96' = 'buffer14'
-- Equation name is 'buffer14', location is LC4_C24, type is buried.
buffer14 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !buffer12 & buffer14
# buffer14 & !_LC2_C26
# !buffer13 & buffer14
# buffer12 & buffer13 & !buffer14 & _LC2_C26;
-- Node name is ':95' = 'buffer15'
-- Equation name is 'buffer15', location is LC1_C24, type is buried.
buffer15 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = buffer15 & !_LC6_C24
# !buffer15 & _LC6_C24;
-- Node name is ':94' = 'buffer16'
-- Equation name is 'buffer16', location is LC2_C29, type is buried.
buffer16 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = buffer16 & !_LC3_C24
# !buffer16 & _LC3_C24;
-- Node name is ':93' = 'buffer17'
-- Equation name is 'buffer17', location is LC1_C23, type is buried.
buffer17 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = !buffer16 & buffer17
# buffer17 & !_LC3_C24
# buffer16 & !buffer17 & _LC3_C24;
-- Node name is ':92' = 'buffer18'
-- Equation name is 'buffer18', location is LC8_C23, type is buried.
buffer18 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = !buffer16 & buffer18
# buffer18 & !_LC3_C24
# !buffer17 & buffer18
# buffer16 & buffer17 & !buffer18 & _LC3_C24;
-- Node name is ':91' = 'buffer19'
-- Equation name is 'buffer19', location is LC7_C23, type is buried.
buffer19 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
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