rs232e.vhd

RS232数据发送器,适合于VHDL的初学者参考

library ieee;
use ieee.std_logic_1164.all;

entity rs232e is
	port(x : in std_logic_vector(7 downto 0);
		 load,clk : in std_logic;
		 tro,empty : out std_logic);
end rs232e;

architecture  rtl of rs232e is
	type state is (t0,t1,t2,t3);
   	signal present_state : state;	
	signal r : std_logic_vector ( 7 downto 0);
	signal parity : std_logic;	
begin
process(clk,load)
	variable cnt : integer range 0 to 9 ;
begin	
	if rising_edge(clk) then 
		case present_state is
			when t0 =>  tro <='1';
						if load='1' then
							present_state<=t1;
							r<=x;
							tro <='0';
							parity<= not (x(0) xor x(1) xor x(2) xor x(3) xor x(4) xor x(5) xor x(6) xor x(7));
							cnt:=1;
							empty<='0';
						else
							 present_state<=t0;
						end if;
			when t1	=>  tro <=r(0);
						r<='0' & r(7 downto 1);
						cnt:=cnt+1;
						if cnt=9 then 
							present_state<=t2;
						else
							present_state<=t1;
						end if;
			when t2 =>	tro <=parity;
						present_state<=t3;
			when t3 =>  tro <='1';
						empty<='1';
						present_state<=t0;
		end case;
	end if;
end process;

end rtl;