📄 control.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port( START :in std_logic;
WAIT_T: in std_logic;
READY: in std_logic;
TEST: in std_logic;
FIRE: in std_logic;
SETUP: in std_logic;
CLK: in std_logic;
SLB,SLT :out std_logic);
end entity;
architecture control_behave of control is
type state_type is(QA,QB,QC,QD,QE,QF,QG);
SIGNAL present_state,next_state:state_type;
begin
nextstate_logic:
process(present_state)
begin
if(START='1')then
case present_state is
when QA=>
SLB<='0';SLT<='0';
if(WAIT_T='0')then
next_state<=QA;
else
next_state<=QB;
end if;
when QB=>
SLB<='0';SLT<='0';
if(READY='0')then
next_state<=QB;
else
next_state<=QC;
end if;
when QC=>
SLB<='0';SLT<='0';
if(TEST='0')then
next_state<=QE;
elsif(TEST='1')then
next_state<=QD;
else
next_state<=QC;
end if;
when QD=>
SLB<='0';SLT<='0';
if(READY='1')then
next_state<=QC;
elsif(FIRE='1')then
next_state<=QG;
else
next_state<=QD;
end if;
when QE=>
SLB<='0';SLT<='0';
if(READY='1')then
next_state<=QC;
elsif(FIRE='1')then
next_state<=QF;
else
next_state<=QE;
end if;
when QF=>
SLB<='1';SLT<='0';
if(SETUP='0')then
next_state<=QF;
else
next_state<=QB;
end if;
when QG=>
SLB<='0';SLT<='1';
if(WAIT_T='0')then
next_state<=QG;
else
next_state<=QA;
end if;
end case;
else
next_state<=QA;
end if;
end process;
state_register:
process(CLK)
begin
if(CLK'event and CLK='1')then
present_state<=next_state;
end if;
end process;
end control_behave;
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