fire_d.vhd

数字密码引爆器的输入描述：1、 在开始输入密码以前的等待状态

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fire_d is
   port( A4:in  std_logic;
		 A1:in  std_logic;
		 A2:in  std_logic;
         A3:in  std_logic;
         CLK:in  std_logic;
         WAIT_T:in std_logic;
         READY:in  std_logic;
         SETUP:in  std_logic;
         FIRE:in  std_logic;
         start:in std_logic;
         light:out std_logic;
         Y:out  std_logic_vector(6 downto 0);
         LT,RT:out std_logic);
  end fire_d;

architecture fire_d_behave of fire_d is
     component seg7
         port(D0,D1,D2,D3 :IN STD_LOGIC;
              Q:out std_logic_vector(6 downto 0));
     end component;

      component kdf
      port( a,clk:in std_logic;
            c,d:out std_logic);
      end component;
     
     component kbianma
         port( EN:in std_logic;
               Y3,Y2,Y1,Y0:out std_logic);
     end component;

     component control
         port( START,WAIT_T,READY,TEST,FIRE,SETUP,CLK: in std_logic;
                 SLB,SLT :out std_logic);
     end component;

     component kcompare
       port( A,B,C,D: IN std_logic;
			 E,F,G,H: IN std_logic;
             CLK:IN std_logic;
        	result: OUT std_logic);
     end component;

     signal E1,E2,E3,E4:std_logic;
     signal B1,B2,B3,B4:std_logic;
	 signal C01,C02,C03,C04:std_logic;
     signal C11,C22,C33,C44:std_logic;
     signal TEST:std_logic;

 begin


	 U1:kdf port map(WAIT_T,CLK,C11,C01);
	 U2:kdf port map(READY,CLK,C22,C02);
	 U3:kdf port map(SETUP,CLK,C33,C03);
	 U4:kdf port map(FIRE,CLK,C44,C04);
	 U5:kdf port map(A1,CLK,B1);
	 U6:kdf port map(A2,CLK,B2);
	 U7:kdf port map(A3,CLK,B3);
	 U8:kdf port map(A4,CLK,B4);


	 U9:kbianma  port map(start,E4,E3,E2,E1);
     U10:kcompare port map(B1,B2,B3,B4,E1,E2,E3,E4,CLK,TEST);
     U11:control  port map(start,C11,C22,TEST,C44,C33,CLK,RT,LT);
     
     U12:seg7 PORT MAP(A1,A2,A3,A4,Y);
     light<='1';

 end fire_d_behave;