📄 seg7.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seg7 is
PORT( D0,D1,D2,D3:IN STD_LOGIC;
Q:OUT STD_LOGIC_vector(6 downto 0));
END seg7;
architecture behave of seg7 is
signal DL:std_logic_vector(3 downto 0);
begin
DL<=D3&D2&D1&D0;
process(DL)
begin
CASE DL IS
WHEN "0000"=> Q<="0111111";
WHEN "0001"=> Q<="0000110";
WHEN "0010"=> Q<="1011011";
WHEN "0011"=> Q<="1001111";
WHEN "0100"=> Q<="1100110";
WHEN "0101"=> Q<="1101101";
WHEN "0110"=> Q<="1111101";
WHEN "0111"=> Q<="0000111";
WHEN "1000"=> Q<="1111111";
WHEN "1001"=> Q<="1101111";
WHEN "1010"=> Q<="1110111";
WHEN "1011"=> Q<="1111100";
WHEN "1100"=> Q<="0111001";
WHEN "1101"=> Q<="1011110";
WHEN "1110"=> Q<="1111001";
WHEN "1111"=> Q<="1110001";
WHEN OTHERS=> Q<="0000000";
END CASE;
end process;
end behave;
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