📄 scan_2.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity SCAN_2 is
PORT(
SCAN_CLK:IN STD_LOGIC;
S,G:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SW,GW:OUT STD_LOGIC;
OUTPUT:OUT STD_LOGIC_vector(3 downto 0));
END SCAN_2 ;
architecture behave of SCAN_2 is
signal TOUT:std_logic;
begin
process(SCAN_CLK)
begin
IF(SCAN_CLK'EVENT AND SCAN_CLK='1')THEN
IF(TOUT='0')THEN
sw <= '1';
gw <= '0';
TOUT<='1';
outPUT<= s;
ELSIF(TOUT='1')THEN
sw <= '0';
gw <= '1';
TOUT<='0';
outPUT <= g;
ELSE
sw <= '1';
gw <= '0';
TOUT<='1';
outPUT<= s;
END IF;
END IF;
end process;
end behave;
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